Merge branch 'master' of https://gitlab.cern.ch/bi/VFC-HD

.gitignore

 *.bak
 *.pyc
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
-Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
-Doc/AlteraDocuments/EMIF_Altera.pdf
-Doc/AlteraDocuments/an520.pdf
-Doc/AlteraDocuments/arriav_handbook.pdf
-Doc/AlteraDocuments/ddr3AlteraDesign.pdf
-Doc/Datasheets/8Gb_DDR3L.pdf
-Hw/Assembly data/
-Hw/EDA-03133-V2-0_project.Annotation
-Hw/EDA-03133-V2-0_project.PrjPCB
-Hw/EDA-03133-V2-0_project.PrjPCBStructure
-Hw/Manufacturing/EDA-03133-V2_mfg.cam
-Hw/PCB-Layout/
-Hw/Schematics/
-Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti
+/Hdl/Simulation/*Project/modelsim/project/*
+!/Hdl/Simulation/*Project/modelsim/project/*.mpf
+/Hdl/Synthesis/*/QuartusPrj/*
+!/Hdl/Synthesis/*/QuartusPrj/*.qpf
+!/Hdl/Synthesis/*/QuartusPrj/*.qsf
+/Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
+/Doc/AlteraDocuments/EMIF_Altera.pdf
+/Doc/AlteraDocuments/an520.pdf
+/Doc/AlteraDocuments/arriav_handbook.pdf
+/Doc/AlteraDocuments/ddr3AlteraDesign.pdf
+/Doc/Datasheets/8Gb_DDR3L.pdf
+/Doc/VfcHd_UserGuides/BI-VFC-HD-V2_0.pdf
+/Hw/Assembly data/
+/Hw/EDA-03133-V2-0_project.Annotation
+/Hw/EDA-03133-V2-0_project.PrjPCB
+/Hw/EDA-03133-V2-0_project.PrjPCBStructure
+/Hw/Manufacturing/EDA-03133-V2_mfg.cam
+/Hw/PCB-Layout/
+/Hw/Schematics/

Hdl/Simulation/BaseProjectSimulation/modelsim/compile.do → Hdl/Simulation/BaseProject/modelsim/compile.do

@@ -77,12 +77,12 @@ compile_verilog $sc work $DUT_PATH/AddrDecoderWbApp.v
 compile_verilog $sc work $DUT_PATH/VfcHdApplication.v
 
 # VFC HD hierarchy:
-compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_dpram.v
-compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_dpram_mod.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/Ip_OpenCores/generic_fifo_dc_gray_mod.v
 compile_verilog $sc work $VFC_PATH/GeneralPurpose/Generic4InputRegs.v
 compile_verilog $sc work $VFC_PATH/GeneralPurpose/Generic4OutputRegs.v
-compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMaster.v
-compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMasterNoBus.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2CMasterWb.v
+compile_verilog $sc work $VFC_PATH/GeneralPurpose/I2cMasterGeneric.v
 compile_verilog $sc work $VFC_PATH/GeneralPurpose/SpiMasterWB.v
 compile_verilog $sc work $VFC_PATH/SystemSpecific/VmeInterface/InterruptManagerWb.v
 compile_verilog $sc work $VFC_PATH/SystemSpecific/VmeInterface/VmeInterfaceWb.v
@@ -104,7 +104,7 @@ compile_verilog $sc work $MODELS_PATH/VfcHd_v2_0.v
 compile_verilog $sc work $MODELS_PATH/VmeBusModule.sv
 
 # Test Bench files:
-compile_verilog $sc work $TB_PATH/tb_BaseProjectAppAcceses.sv
+compile_verilog $sc work $TB_PATH/tb_BaseProject.sv
 
 ###############################################
 # Top file

Hdl/Simulation/BaseProjectSimulation/modelsim/simulate.do → Hdl/Simulation/BaseProject/modelsim/simulate.do

@@ -15,7 +15,7 @@ echo ""
 echo "Starting Simulation..."
 echo ""
 
-vsim -gui -novopt work.tb_BaseProjectAppAcceses
+vsim -gui -novopt work.tb_BaseProject
 do waveforms.do
 run -all
 

Sw/Python/Class_VfcHd_System.py

@@ -15,7 +15,7 @@ def HexN(Value, N=8):
 class VfcHd_System:
 
     '############################################################################################################'
-    '####                                                                                                    ####'                                                                                          
+    '####                                                                                                    ####'
     '####                              **** PLEASE, DO NOT MODIFY THIS FILE ****                             ####'
     '####                                                                                                    ####'
     '#### Note!! This is the PARENT class containing all attributes and methods related to the System module ####'