Skip to content
GitLab
Projects
Groups
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Sign in
Toggle navigation
Menu
Open sidebar
Dimitris Lampridis
VFC-HD
Commits
cbdabb7f
Commit
cbdabb7f
authored
Nov 06, 2016
by
Manoel Barros Marin
Browse files
Merge branch 'master' of
https://gitlab.cern.ch/bi/VFC-HD
parents
abca22fd
decee13e
Changes
7
Expand all
Hide whitespace changes
Inline
Side-by-side
.gitignore
View file @
cbdabb7f
*.bak
*.pyc
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@app/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@addr@decoder@w@b@sys/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@input@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@generic4@output@regs/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@master/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@i2@c@slave/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@iir1st@order@lp/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@interrupt@manager@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@period@counter/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@spi@master@w@b/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@unique@id@reader/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@application/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@system/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd@top/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vfc@hd_v2_0/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@bus@module/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/@vme@interface@wb/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/fmc_test_wrapper/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_dpram/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/generic_fifo_dc_gray/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/si57x/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/sn74vmeh22501/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/tb_@vfc@basic@access/verilog.rw64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.asm64
Hdl/Simulation/BasicVmeAccesses/modelsim/project/work/user_io_checker/verilog.rw64
Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
Doc/AlteraDocuments/EMIF_Altera.pdf
Doc/AlteraDocuments/an520.pdf
Doc/AlteraDocuments/arriav_handbook.pdf
Doc/AlteraDocuments/ddr3AlteraDesign.pdf
Doc/Datasheets/8Gb_DDR3L.pdf
Hw/Assembly data/
Hw/EDA-03133-V2-0_project.Annotation
Hw/EDA-03133-V2-0_project.PrjPCB
Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/Manufacturing/EDA-03133-V2_mfg.cam
Hw/PCB-Layout/
Hw/Schematics/
Hdl/Simulation/BasicVmeAccesses/modelsim/project/BasicVmeAccesses.cr.mti
/Hdl/Simulation/*Project/modelsim/project/*
!/Hdl/Simulation/*Project/modelsim/project/*.mpf
/Hdl/Synthesis/*/QuartusPrj/*
!/Hdl/Synthesis/*/QuartusPrj/*.qpf
!/Hdl/Synthesis/*/QuartusPrj/*.qsf
/Doc/AlteraDocuments/Arria_V_GX_GT_SX_ST_Schematic_Review_Worksheet.doc
/Doc/AlteraDocuments/EMIF_Altera.pdf
/Doc/AlteraDocuments/an520.pdf
/Doc/AlteraDocuments/arriav_handbook.pdf
/Doc/AlteraDocuments/ddr3AlteraDesign.pdf
/Doc/Datasheets/8Gb_DDR3L.pdf
/Doc/VfcHd_UserGuides/BI-VFC-HD-V2_0.pdf
/Hw/Assembly data/
/Hw/EDA-03133-V2-0_project.Annotation
/Hw/EDA-03133-V2-0_project.PrjPCB
/Hw/EDA-03133-V2-0_project.PrjPCBStructure
/Hw/Manufacturing/EDA-03133-V2_mfg.cam
/Hw/PCB-Layout/
/Hw/Schematics/
Hdl/Simulation/BaseProject
Simulation
/modelsim/compile.do
→
Hdl/Simulation/BaseProject/modelsim/compile.do
View file @
cbdabb7f
...
...
@@ -77,12 +77,12 @@ compile_verilog $sc work $DUT_PATH/AddrDecoderWbApp.v
compile_verilog
$sc
work
$DUT_PATH
/
VfcHdApplication
.
v
# VFC HD hierarchy:
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/
Ip_OpenCores
/
generic_dpram
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/
Ip_OpenCores
/
generic_fifo_dc_gray
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/
Ip_OpenCores
/
generic_dpram
_mod
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/
Ip_OpenCores
/
generic_fifo_dc_gray
_mod
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/
Generic4InputRegs
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/
Generic4OutputRegs
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/I2CMaster.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/I2
C
Master
NoBus
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/I2CMaster
Wb
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/I2
c
Master
Generic
.
v
compile_verilog
$sc
work
$VFC_PATH
/
GeneralPurpose
/SpiMasterWB.
v
compile_verilog
$sc
work
$VFC_PATH
/
SystemSpecific
/
VmeInterface
/InterruptManagerWb.
v
compile_verilog
$sc
work
$VFC_PATH
/
SystemSpecific
/
VmeInterface
/
VmeInterfaceWb
.
v
...
...
@@ -104,7 +104,7 @@ compile_verilog $sc work $MODELS_PATH/VfcHd_v2_0.v
compile_verilog
$sc
work
$MODELS_PATH
/
VmeBusModule
.
sv
# Test Bench files:
compile_verilog
$sc
work
$TB_PATH
/
tb_BaseProject
AppAcceses
.
sv
compile_verilog
$sc
work
$TB_PATH
/
tb_BaseProject
.
sv
###############################################
# Top file
...
...
Hdl/Simulation/BaseProject
Simulation
/modelsim/project/BaseProject_sim.mpf
→
Hdl/Simulation/BaseProject/modelsim/project/BaseProject_sim.mpf
View file @
cbdabb7f
File moved
Hdl/Simulation/BaseProject
Simulation
/modelsim/simulate.do
→
Hdl/Simulation/BaseProject/modelsim/simulate.do
View file @
cbdabb7f
...
...
@@ -15,7 +15,7 @@ echo ""
echo
"Starting Simulation..."
echo
""
vsim
-
gui
-
novopt
work
.
tb_BaseProject
AppAcceses
vsim
-
gui
-
novopt
work
.
tb_BaseProject
do
waveforms
.
do
run
-
all
...
...
Hdl/Simulation/BaseProject
Simulation
/modelsim/waveforms.do
→
Hdl/Simulation/BaseProject/modelsim/waveforms.do
View file @
cbdabb7f
This diff is collapsed.
Click to expand it.
Hdl/Simulation/BaseProject
Simulation
/tb_BaseProject.sv
→
Hdl/Simulation/BaseProject/tb_BaseProject.sv
View file @
cbdabb7f
File moved
Sw/Python/Class_VfcHd_System.py
View file @
cbdabb7f
...
...
@@ -15,7 +15,7 @@ def HexN(Value, N=8):
class
VfcHd_System
:
'############################################################################################################'
'#### ####'
'#### ####'
'#### **** PLEASE, DO NOT MODIFY THIS FILE **** ####'
'#### ####'
'#### Note!! This is the PARENT class containing all attributes and methods related to the System module ####'
...
...
Write
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment