- Added power up reset

Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v

@@ -118,9 +118,11 @@ module VfcHdSystem
 //Declarations
 //****************************
 
+reg  [15:0] ResetShiftReg_rnd16 = 16'h0000;
+reg  Reset_rq;
+reg  [1:0] ResetWb_x2;
 wire VmeAccess, VmeDtAck_n;
 wire [7:1] VmeIrq_nb7;
-reg [1:0] VmeSysResetWb_d2 = 2'h0;
 wire WbCyc, WbStb, WbWe, WbAck;  
 wire [21:0] WbAdr_b22; 
 wire [31:0] WbDatMiSo_b32, WbDatMoSi_b32;
@@ -128,7 +130,7 @@ wire IntEnable, IntModeRoRa, IntSourceToRead, NewIntRequest;
 wire [2:0] IntLevel_b3;
 wire [7:0] IntVector_b8; 
 wire [31:0] IntRequestBus_ab32;
-reg [1:0] VmeSysReset_d2 = 2'h0;
+reg [1:0] VmeSysReset_rnx2 = 2'h0;
 wire WbAckIntManager, WbStbIntManager;
 wire [31:0] WbDatMiSoIntManager_b32;
 wire WbAckSpiMaster, WbStbSpiMaster;
@@ -149,7 +151,6 @@ wire VmeGap_n; //need to be accessed from the I2C exp
 wire WbAckI2cWrProm, WbStbI2cWrProm; 	
 wire [31:0] WbDatI2cWrProm_b32;
 
-
 //****************************
 //Clocking
 //****************************
@@ -159,15 +160,15 @@ wire [31:0] WbDatI2cWrProm_b32;
 
 wire Clk_k = GbitTrxClkRefR_ik;
 
-
 //****************************
 //Reset
 //****************************
 
-always @(posedge Clk_k) VmeSysReset_d2 <= #1 {VmeSysReset_d2[0], ~VmeSysReset_irn};
-wire a_Reset_rq = VmeSysReset_d2[1];
-always @(posedge WbClk_ik) VmeSysResetWb_d2 <= #1 {VmeSysResetWb_d2[0], ~VmeSysReset_irn};
-assign Reset_orqp = VmeSysResetWb_d2[1];
+always @(posedge Clk_k) ResetShiftReg_rnd16  <= #1  {ResetShiftReg_rnd16[14:0],1'b1};
+always @(posedge Clk_k) VmeSysReset_rnx2     <= #1  {VmeSysReset_rnx2[0], VmeSysReset_irn};
+always @(posedge Clk_k) Reset_rq             <= #1 ~(VmeSysReset_rnx2[1] && ResetShiftReg_rnd16[15]);
+always @(posedge WbClk_ik) ResetWb_x2        <= #1  {ResetWb_x2[0], Reset_rq};
+assign Reset_orqp = ResetWb_x2[1];
 
 //****************************
 //VME interface & Wishbone Master
@@ -187,7 +188,7 @@ VmeInterfaceWb #( .g_LowestGaAddressBit(24), .g_ClocksIn2us(250_000) )
    i_VmeInterfaceWb
    (
       .Clk_ik(Clk_k),
-      .Rst_irq(a_Reset_rq),  
+      .Rst_irq(Reset_rq),  
       .VmeGa_ib5(VmeGa_b5),
       .VmeGap_in(VmeGap_n),
       .VmeAs_in(VmeAs_in),
@@ -259,7 +260,7 @@ InterruptManagerWb #(
       .g_ReleaseMonth_b8(g_SystemReleaseMonth_b8), 
       .g_ReleaseYear_b8(g_SystemReleaseYear_b8))
    i_InterruptManagerWb(	
-      .Rst_irq(a_Reset_rq),
+      .Rst_irq(Reset_rq),
       .Clk_ik(Clk_k),
       .Cyc_i(WbCyc),
       .Stb_i(WbStbIntManager),
@@ -275,13 +276,12 @@ InterruptManagerWb #(
       .IntVector_ob8(IntVector_b8),
       .IntSourceToRead_o(IntSourceToRead), 
       .NewIntRequest_oqp(NewIntRequest));   
-    
   
 //****************************
 //SPI INTERFACES: Vadj pot, ADC
 //****************************
 SpiMasterWB i_SpiMaster(
-		.Rst_irq(a_Reset_rq),
+		.Rst_irq(Reset_rq),
 		.Clk_ik(Clk_k),
 		.Cyc_i(WbCyc),
 		.Stb_i(WbStbSpiMaster),
@@ -310,7 +310,7 @@ assign VAdcSclk_ok	 = SpiClk_k;
 
 UniqueIdReader #(.g_OneUsClkCycles(125)) 
 	i_UniqueIdReader(   
-		.Rst_irq(a_Reset_rq),
+		.Rst_irq(Reset_rq),
 		.Clk_ik(Clk_k),
 		.Cyc_i(WbCyc),
 		.Stb_i(WbStbUniqueIdReader),
@@ -343,7 +343,7 @@ UniqueIdReader #(.g_OneUsClkCycles(125))
 I2CMaster #(.g_CycleLenght(10'd256))
 	i_I2cIoExpAndMux
 	(   
-	.Rst_irq(a_Reset_rq),
+	.Rst_irq(Reset_rq),
 	.Clk_ik(Clk_k),
 	.Cyc_i(WbCyc),
 	.Stb_i(WbStbI2cIoExpAndMux),
@@ -354,7 +354,6 @@ I2CMaster #(.g_CycleLenght(10'd256))
 	.Ack_oa(WbAckI2cIoExpAndMux),
     .Scl_ioz(I2cMuxScl_ok),
 	.Sda_ioz(I2cMuxSda_io));
-
 	
 //****************************
 //IO EXP and MUX
@@ -363,7 +362,7 @@ I2CMaster #(.g_CycleLenght(10'd256))
 I2CMaster #(.g_CycleLenght(10'd256))
 	i_I2cWrProm
 	(   
-	.Rst_irq(a_Reset_rq),
+	.Rst_irq(Reset_rq),
 	.Clk_ik(Clk_k),
 	.Cyc_i(WbCyc),
 	.Stb_i(WbStbI2cWrProm),
@@ -375,7 +374,6 @@ I2CMaster #(.g_CycleLenght(10'd256))
     .Scl_ioz(WrPromScl_ok),
 	.Sda_ioz(WrPromSda_io));
 	
-	
 //****************************
 //SYS <=> APP Wishbone interface 	
 //****************************      
@@ -402,6 +400,4 @@ always @(posedge Clk_k) begin
    if (WbAckAppSlaveBus_xd2[1]&&~WbAckAppSlaveBus) WbDatAppSlaveBus_b32 <= #1 WbMasterDat_ib32; 
 end
    
-  
-   
 endmodule
\ No newline at end of file

Hdl/Synthesis/BaseProject/QuartusPrj/VfcHd_BaseProject.qsf

@@ -648,4 +648,6 @@ set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/Vme
 set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v
 set_global_assignment -name VERILOG_FILE ../../../FpgaModules/SystemSpecific/VfcHdSystem.v
 set_global_assignment -name VERILOG_FILE ../../../FpgaModules/VfcHdTop.v
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "NORMAL COMPILATION"
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file