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Work in progress: preparing the structure of the project

parent b40c90cc
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.gitignore 0 → 100644
View file @ e5ecd234
Doc/AlteraDocuments/
Doc/Datasheets/
Hw/Assembly data/
Hw/EDA-03133-V2-0_project.Annotation
Hw/EDA-03133-V2-0_project.PrjPCB
Hw/EDA-03133-V2-0_project.PrjPCBStructure
Hw/EDA-03133-V2-0_sch.pdf
Hw/Manufacturing/
Hw/PCB-Layout/
Hw/Schematics/
Hdl/BE_BI_verilog_template.v 0 → 100644
View file @ e5ecd234
//============================================================================================\\
//################################## Module Information ##################################\\
//============================================================================================\\
//
// Company: CERN (BE-BI)
//
// File Name: <ModuleName>.v
//
// File versions history:
//
// DATE VERSION AUTHOR DESCRIPTION
// - <date> <version> <author> <description>
//
// Language: Verilog 2005
//
// Targeted device:
//
// - Vendor: <FPGA manufacturer if vendor specific code>
// - Model: <FPGA Model if model specific>
//
// Description:
//
// <Brief description of the module.>
//
//============================================================================================\\
//############################################################################################\\
//============================================================================================\\
`timescale 1ns/100ps
module ModuleName
//==================================== Global Parameters ===================================\\
#( parameter g_Parameter1 = 32'hfac3_babe,
g_Parameter2 = 16'hcafe)
//======================================== I/O ports =======================================\\
(
//==== Clocks & Resets ====\\
input Clock_ik,
input Reset_iran, //Comment: Just a comment about the functionality
input Reset_ir,
//==== <Section> ====\\
input Input1_i,
output [31:0] Output_ob8, //Comment: (a) Another comment about the functionality
// (b) Second comment about the inout
output reg [31:0] Output_oqb32,
// <Sub section>:
inout InOut_io,
//==== <Section> ====\\
output Output3_oa
);
//======================================= Declarations =====================================\\
//==== Local parameters ====\\
localparam c_MyParam = 16'hcaca,
c_YourParam = 16'ac1d;
// FSM:
localparam s_Idle = 3'b001,
s_State1 = 3'b010,
s_State2 = 3'b100;
//==== Wires & Regs ====\\
wire Wire1;
reg [7:0] MyCounter_c8;
reg [7:0] YourCounter_c8;
// FSM:
reg [ 2:0] State_qb3, NextState_ab3;
//======================================= User Logic =======================================\\
//==== Example of Secuential logic ====\\
// Example of synchronous logic with asynchronous reset:
always @(posedge Clock_ik or negedge Reset_iran)
if (~Reset_iran) begin
MyCounter_c8 <= #1 8'h0;
end else if (Reset_ir) begin
MyCounter_c8 <= #1 8'h0;
end else begin
MyCounter_c8 <= #1 MyCounter_c8 + 1'b1;
end
// Example of synchronous logic with synchronous reset:
always @(posedge Clock_ik)
if (Reset_ir) begin
YourCounter_c8 <= #1 8'h0;
end else begin
YourCounter_c8 <= #1 YourCounter_c8 + 1'b1;
end
//==== Example of FSM ====\\
always @(posedge Clock_ik) State_qb3 <= #1 Reset_ir ? s_Idle : NextState_ab3;
always @* begin
NextState_ab3 = State_qb3;
case(State_qb3)
s_Idle: begin
if (Condition1) begin
NextState_ab3 = s_State1;
end
end
s_State1: begin
if (Condition2) begin
NextState_ab3 = s_State2;
end else if (Condition0) begin
NextState_ab3 = s_Idle;
end
end
s_State2: begin
if (Condition0) begin
NextState_ab3 = s_Idle;
end
end
default: begin
NextState_ab3 = s_Idle;
end
endcase
end
always @(posedge Clock_ik)
if (Reset_ir) begin
IdleAction_q <= #1 4'b0;
State1Action_q <= #1 4'b0;
State2Action_q <= #1 4'b0;
end else begin
case(State_qb3)
s_Idle: begin
IdleAction_q <= #1 4'b0;
State1Action_q <= #1 4'b0;
State2Action_q <= #1 4'b0;
end
s_State1: begin
State1Action_q <= #1 4'b0;
end
s_State2: begin
State2Action_q <= #1 4'b0;
end
endcase
end
endmodule
\ No newline at end of file
Hdl/FpgaModules/VfcHdTop.v 0 → 100644
View file @ e5ecd234
`timescale 1ns/100ps
module VfcHdTop
(
//VME interface
input VmeAs_in,
input [5:0] VmeAm_ib6,
inout [31:1] VmeA_iob31,
inout VmeLWord_ion,
output VmeAOe_oen,
output VmeADir_o,
input [1:0] VmeDs_inb2,
input VmeWrite_in,
inout [31:0] VmeD_iob32,
output VmeDOe_oen,
output VmeDDir_o,
output VmeDtAckOe_o,
output [7:1] VmeIrq_ob7,
input VmeIack_in,
input VmeIackIn_in,
output VmeIackOut_on,
input VmeSysClk_ik,
input VmeSysReset_irn,
//SFP Gbit
input [4:1] AppSfpRx_ib4, //Differential
output [4:1] AppSfpTx_ob4, //Differential
input BstSfpRx_i, //Differential
output BstSfpTx_o, //Differential
input EthSfpRx_i, //Differential
output EthSfpTx_o, //Differential
//DDR3
output [15:0] Ddr3AA_ob16,
output [2:0] Ddr3ABa_ob3,
output Ddr3ACk_ok, //differential signals
output [1:0] Ddr3ACkE_oeb2,
output [1:0] Ddr3ACs_onb2,
output Ddr3ALdm_o,
output Ddr3AUdm_o,
output [1:0] Ddr3AOdt_ob2,
output Ddr3ARas_on,
output Ddr3ACas_on,
output Ddr3AWe_on,
output Ddr3AReset_orn,
inout [15:0] Ddr3ADq_iob16,
inout Ddr3ALdqs_io, //differential signals
inout Ddr3AUdqs_io, //differential signals
output [15:0] Ddr3BA_ob16,
output [2:0] Ddr3BBa_ob3,
output Ddr3BCk_ok, //differential signals
output [1:0] Ddr3BCkE_oeb2,
output [1:0] Ddr3BCs_onb2,
output Ddr3BLdm_o,
output Ddr3BUdm_o,
output [1:0] Ddr3BOdt_ob2,
output Ddr3BRas_on,
output Ddr3BCas_on,
output Ddr3BWe_on,
output Ddr3BReset_orn,
inout [15:0] Ddr3BDq_iob16,
inout Ddr3BLdqs_io, //differential signals
inout Ddr3BUdqs_io, //differential signals
//TestIo
inout TestIo1_io,
inout TestIo2_io,
//I2C Mux and IO expanders
inout I2cMuxSda_io,
output I2cMuxScl_ok,
input I2CMuxIntN0_in,
input I2CMuxIntN1_in,
input I2CIoExpIntApp12_in,
input I2CIoExpIntApp34_in,
input I2CIoExpIntBstEth_in,
input I2CIoExpIntBlmIn_in,
//BST
input BstDataIn_i,
input CdrClkOut_ik,
input CdrDataOut_i,
//ADC Voltage monitoring
input VAdcDout_i,
output VAdcDin_o,
output VAdcCs_o,
output VAdcSclk_ok,
//FMC connector
inout [33:0]FmcLaP_iob34,
inout [33:0]FmcLaN_iob34,
inout [23:0]FmcHaP_iob24,
inout [23:0]FmcHaN_iob24,
inout [21:0]FmcHbP_iob22,
inout [21:0]FmcHbN_iob22,
input FmcPrsntM2C_in,
output FmcTck_ok,
output FmcTms_o,
output FmcTdi_o,
input FmcTdo_i,
output FmcTrstL_orn,
output FmcScl_ok,
inout FmcSda_io,
input FmcPgM2C_in,
output FmcPgC2M_on,
input FmcClk0M2CCmos_ik,
input FmcClk1M2CCmos_ik,
input FmcClk2Bidir_ik, //differential signal
input FmcClk3Bidir_ik, //differential signal
input FmcClkDir_i,
output [9:0] FmcDpC2M_ob10, //diff output
input [9:0] FmcDpM2C_ib10,
input FmcGbtClk0M2CLeft_ik, //differential signal
input FmcGbtClk1M2CLeft_ik, //differential signal
input FmcGbtClk0M2CRight_ik, //differential signal
input FmcGbtClk1M2CRight_ik, //differential signal
//Clock sources and control
output OeSi57x_oe,
input Si57xClk_ik,
output ClkFb_ok,
input ClkFb_ik,
input Clk20VCOx_ik,
output PllDac20Sync_o,
output PllDac25Sync_o,
output PllDacSclk_ok,
output PllDacDin_o,
inout PllRefSda_io,
output PllRefScl_ok,
inout PllRefInt_i,
output PllSourceMuxOut_ok,
input PllRefClkOut_ik, //Differential reference for the Gbit lines
input GbitTrxClkRefR_ik, //Differential reference for the Gbit lines
//Fmc Voltage control
output VadjCs_o,
output VadjSclk_ok,
output VadjDin_o,
output VfmcEnableN_oen,
//SW1
input [4:0] NoGa_ib5,
input UseGa_i,
input [1:0] Switch_ib2,
//Pcb Revision resistor network
input [7:0] PcbRev_ib7,
//P2 RTM
inout [19:0] P2DataP_iob20, //the 0 is a clock capable input
inout [19:0] P2DataN_iob20,
//P0 Timing
input [7:0] P0HwHighByte_ib8,
input [7:0] P0HwLowByte_ib8,
output DaisyChain1Cntrl_o,
output DaisyChain2Cntrl_o,
input VmeP0BunchClk_ik,
input VmeP0Tclk_ik,
//WR PROM
inout WrPromSda_io,
output WrPromScl_ok,
//GPIO
inout [4:1] GpIo_iob4,
//Specials
input PushButtonN_in,
inout TempIdDq_ioz,
output ResetFpgaConfigN_orn
);
//@@@@@@@@@@@@@@@@@@@
//WIRE DECLARATIONS
//@@@@@@@@@@@@@@@@@@@
wire WbClk_k;
wire Wb1Cyc, Wb1Stb, Wb1Wr, Wb1Ack;
wire [24:0] Wb1Adr_b25;
wire [31:0] Wb1DatMosi_b32, Wb1DatMiso_b32;
wire Wb2Cyc, Wb2Stb, Wb2Wr, Wb2Ack;
wire [24:0] Wb2Adr_b25;
wire [31:0] Wb2DatMosi_b32, Wb2DatMiso_b32;
wire [1:0] TopLed_b2;
wire [3:0] BottomLed_b4;
wire BstOn, BunchClk_k, TurnClk_p;
wire [5:0] BstByteAddress_b5;
wire [7:0] BstByte_b8;
wire [23:0] InterruptRequest_pb24;
wire StreamerClk_k, SreamerDav, StreamerPckt, StreamerWait;
wire [31:0] StreamerData_b32;
wire GpIo1DirOut, GpIo2DirOut, GpIo34DirOut;
wire Reset_rqp, ResetRequest_qp;
//@@@@@@@@@@@@@@@@@@@
//SYSTEM MODULE
//@@@@@@@@@@@@@@@@@@@
VfcHdSystem
#(
.g_SystemVersion_b8(8'ha0),
.g_SystemReleaseDay_b8(8'h12),
.g_SystemReleaseMonth_b8(8'h06),
.g_SystemReleaseYear_b8(8'h15)
)
i_VfcHdSystem(
//DIRECT CONNECTIONS TO THE FPGA IOs
// VME interface
.VmeAs_in(VmeAs_in),
.VmeAm_ib6(VmeAm_ib6),
.VmeA_iob31(VmeA_iob31),
.VmeLWord_ion(VmeLWord_ion),
.VmeAOe_oen(VmeAOe_oen),
.VmeADir_o(VmeADir_o),
.VmeDs_inb2(VmeDs_inb2),
.VmeWrite_in(VmeWrite_in),
.VmeD_iob32(VmeD_iob32),
.VmeDOe_oen(VmeDOe_oen),
.VmeDDir_o(VmeDDir_o),
.VmeDtAckOe_o(VmeDtAckOe_o),
.VmeIrq_ob7(VmeIrq_ob7),
.VmeIack_in(VmeIack_in),
.VmeIackIn_in(VmeIackIn_in),
.VmeIackOut_on(VmeIackOut_on),
.VmeSysClk_ik(VmeSysClk_ik),
.VmeSysReset_irn(VmeSysReset_irn),
// .BstSfpRx_i(BstSfpRx_i),
// .BstSfpTx_o(BstSfpTx_o),
// .EthSfpRx_i(EthSfpRx_i),
// .EthSfpTx_o(EthSfpTx_o),
.I2cMuxSda_io(I2cMuxSda_io),
.I2cMuxScl_ok(I2cMuxScl_ok),
.I2CMuxIntN0_in(I2CMuxIntN0_in),
.I2CMuxIntN1_in(I2CMuxIntN1_in),
.I2CIoExpIntApp12_in(I2CIoExpIntApp12_in),
.I2CIoExpIntApp34_in(I2CIoExpIntApp34_in),
.I2CIoExpIntBstEth_in(I2CIoExpIntBstEth_in),
.I2CIoExpIntBlmIn_in(I2CIoExpIntBlmIn_in),
.BstDataIn_i(BstDataIn_i),
.CdrClkOut_ik(CdrClkOut_ik),
.CdrDataOut_i(CdrDataOut_i),
.VAdcDout_i(VAdcDout_i),
.VAdcDin_o(VAdcDin_o),
.VAdcCs_o(VAdcCs_o),
.VAdcSclk_ok(VAdcSclk_ok),
.GbitTrxClkRefR_ik(GbitTrxClkRefR_ik),
.VadjCs_o(VadjCs_o),
.VadjSclk_ok(VadjSclk_ok),
.VadjDin_o(VadjDin_o),
.VfmcEnableN_oen(VfmcEnableN_oen),
.NoGa_ib5(NoGa_ib5),
.UseGa_i(UseGa_i),
.PcbRev_ib7(PcbRev_ib7),
.WrPromSda_io(WrPromSda_io),
.WrPromScl_ok(WrPromScl_ok),
.TempIdDq_ioz(TempIdDq_ioz),
.ResetFpgaConfigN_orn(ResetFpgaConfigN_orn),
//CONNECTIONS SYSTAM<->APPLICATION
.Reset_orqp(Reset_rqp),
.ResetRequest_iqp(ResetRequest_qp),
.WbClk_ik(WbClk_k),
.WbMasterCyc_o(Wb1Cyc),
.WbMasterStb_o(Wb1Stb),
.WbMasterAdr_ob25(Wb1Adr_b25), //The actual width of the address bus is set to 21 for the moment: top bits stuck to 0
.WbMasterWr_o(Wb1Wr),
.WbMasterDat_ob32(Wb1DatMosi_b32),
.WbMasterDat_ib32(Wb1DatMiso_b32),
.WbMasterAck_i(Wb1Ack),
.WbSlaveCyc_i(Wb2Cyc),
.WbSlaveStb_i(Wb2Stb),
.WbSlaveAdr_ib25(Wb2Adr_b25),
.WbSlaveWr_i(Wb2Wr),
.WbSlaveDat_ib32(Wb2DatMosi_b32),
.WbSlaveDat_ob32(Wb2DatMiso_b32),
.WbSlaveAck_o(Wb2Ack),
.TopLed_ib2(TopLed_b2),
.BottomLed_ib4(BottomLed_b4),
.BstOn_o(BstOn),
.BunchClk_ok(BunchClk_k),
.TurnClk_op(TurnClk_p),
.BstByteAddress_ob5(BstByteAddress_b5),
.BstByte_ob8(BstByte_b8),
.InterruptRequest_ipb24(InterruptRequest_pb24),
.StreamerClk_ik(StreamerClk_k),
.StreamerData_ib32(StreamerData_b32),
.SreamerDav_i(SreamerDav),
.StreamerPckt_i(StreamerPckt),
.StreamerWait_o(StreamerWait),
.GpIo1DirOut_i(GpIo1DirOut),
.GpIo2DirOut_i(GpIo2DirOut),
.GpIo34DirOut_i(GpIo34DirOut));
//@@@@@@@@@@@@@@@@@@@
//APPLICATION MODULE
//@@@@@@@@@@@@@@@@@@@
VfcHdApplication i_VfcHdApplication
(
//DIRECT CONNECTIONS TO THE FPGA IOs
.BstSfpRx_i(BstSfpRx_i),
.BstSfpTx_o(BstSfpTx_o),
.EthSfpRx_i(EthSfpRx_i),
.EthSfpTx_o(EthSfpTx_o),
//---
/* .AppSfpRx_ib4(AppSfpRx_ib4),
.AppSfpTx_ob4(AppSfpTx_ob4),
.DdrBa_ob3(DdrBa_ob3),
.DdrDm_ob8(DdrDm_ob8),
.DdrDqs_iob8(DdrDqs_iob8),
.DdrDq_iob64(DdrDq_iob64),
.DdrA_ob16(DdrA_ob16),
.DdrCk_okb2(DdrCk_okb2),
.DdrCkE_ohb2(DdrCkE_ohb2),
.DdrReset_orn(DdrReset_orn),
.DdrRas_on(DdrRas_on),
.DdrCas_on(DdrCas_on),
.DdrWe_on(DdrWe_on),
.DdrCs_onb2(DdrCs_onb2),
.DdrOdt_ob2(DdrOdt_ob2),
.DdrTempEvent_in(DdrTempEvent_in),
.DdrI2cScl_ok(DdrI2cScl_ok),
.DdrI2cSda_io(DdrI2cSda_io), */
.TestIo1_io(TestIo1_io),
.TestIo2_io(TestIo2_io),
.FmcLaP_iob34(FmcLaP_iob34),
.FmcLaN_iob34(FmcLaN_iob34),
.FmcHaP_iob24(FmcHaP_iob24),
.FmcHaN_iob24(FmcHaN_iob24),
.FmcHbP_iob22(FmcHbP_iob22),
.FmcHbN_iob22(FmcHbN_iob22),
.FmcPrsntM2C_in(FmcPrsntM2C_in),
.FmcTck_ok(FmcTck_ok),
.FmcTms_o(FmcTms_o),
.FmcTdi_o(FmcTdi_o),
.FmcTdo_i(FmcTdo_i),
.FmcTrstL_orn(FmcTrstL_orn),
.FmcScl_ok(FmcScl_ok),
.FmcSda_io(FmcSda_io),
.FmcPgM2C_in(FmcPgM2C_in),
.FmcPgC2M_on(FmcPgC2M_on),
.FmcClk0M2CCmos_ik(FmcClk0M2CCmos_ik),
.FmcClk1M2CCmos_ik(FmcClk1M2CCmos_ik),
.FmcClk2Bidir_ik(FmcClk2Bidir_ik),
.FmcClk3Bidir_ik(FmcClk3Bidir_ik),
.FmcClkDir_i(FmcClkDir_i),
.FmcDpC2M_ob10(FmcDpC2M_ob10),
.FmcDpM2C_ib10(FmcDpM2C_ib10),
.FmcGbtClk0M2CLeft_ik(FmcGbtClk0M2CLeft_ik),
.FmcGbtClk1M2CLeft_ik(FmcGbtClk1M2CLeft_ik),
.FmcGbtClk0M2CRight_ik(FmcGbtClk0M2CRight_ik),
.FmcGbtClk1M2CRight_ik(FmcGbtClk1M2CRight_ik),
.OeSi57x_oe(OeSi57x_oe),
.Si57xClk_ik(Si57xClk_ik),
.ClkFb_ok(ClkFb_ok),
.ClkFb_ik(ClkFb_ik),
.Clk20VCOx_ik(Clk20VCOx_ik),
.PllDac20Sync_o(PllDac20Sync_o),
.PllDac25Sync_o(PllDac25Sync_o),
.PllDacSclk_ok(PllDacSclk_ok),
.PllDacDin_o(PllDacDin_o),
.PllRefSda_io(PllRefSda_io),
.PllRefScl_ok(PllRefScl_ok),
.PllRefInt_i(PllRefInt_i),
.PllSourceMuxOut_ok(PllSourceMuxOut_ok),
.PllRefClkOut_ik(PllRefClkOut_ik),
.GbitTrxClkRefR_ik(GbitTrxClkRefR_ik),
.Switch_ib2(Switch_ib2),
.P2DataP_iob20(P2DataP_iob20),
.P2DataN_iob20(P2DataN_iob20),
.P0HwHighByte_ib8(P0HwHighByte_ib8),
.P0HwLowByte_ib8(P0HwLowByte_ib8),
.P0BlmIn_ib8(P0BlmIn_ib8),
.DaisyChain1Cntrl_o(DaisyChain1Cntrl_o),
.DaisyChain2Cntrl_o(DaisyChain2Cntrl_o),
.VmeP0BunchClk_ik(VmeP0BunchClk_ik),
.VmeP0Tclk_ik(VmeP0Tclk_ik),
.GpIo_iob4(GpIo_iob4),
.PushButtonN_in(PushButtonN_in),
//CONNECTIONS SYSTAM<->APPLICATION
.Reset_irqp(Reset_rqp),
.ResetRequest_oqp(ResetRequest_qp),
.WbClk_ok(WbClk_k),
.WbSlaveCyc_i(Wb1Cyc),
.WbSlaveStb_i(Wb1Stb),
.WbSlaveAdr_ib25(Wb1Adr_b25),
.WbSlaveWr_i(Wb1Wr),
.WbSlaveDat_ib32(Wb1DatMosi_b32),
.WbSlaveDat_ob32(Wb1DatMiso_b32),
.WbSlaveAck_o(Wb1Ack),
.WbMasterCyc_o(Wb2Cyc),
.WbMasterStb_o(Wb2Stb),
.WbMasterAdr_ob25(Wb2Adr_b25),
.WbMasterWr_o(Wb2Wr),
.WbMasterDat_ob32(Wb2DatMosi_b32),
.WbMasterDat_ib32(Wb2DatMiso_b32),
.WbMasterAck_i(Wb2Ack),
.TopLed_ob2(TopLed_b2),
.BottomLed_ob4(BottomLed_b4),
.BstOn_i(BstOn),
.BunchClk_ik(BunchClk_k),
.TurnClk_ip(TurnClk_p),
.BstByteAddress_ib5(BstByteAddress_b5),
.BstByte_ib8(BstByte_b8),
.InterruptRequest_opb24(InterruptRequest_pb24),
.StreamerClk_ok(StreamerClk_k),
.StreamerData_ob32(StreamerData_b32),
.SreamerDav_o(SreamerDav),
.StreamerPckt_o(StreamerPckt),
.StreamerWait_i(StreamerWait),
.GpIo1DirOut_o(GpIo1DirOut),
.GpIo2DirOut_o(GpIo2DirOut),
.GpIo34DirOut_o(GpIo34DirOut));
endmodule
\ No newline at end of file
Hdl/Simulation/BE_BI_verilog_testbench_template.v 0 → 100644
View file @ e5ecd234
//============================================================================================\\
//################################ Test Bench Information ################################\\
//============================================================================================\\
//
// Company: CERN (BE-BI)
//
// File Name: <ModuleName_tb>.v
//
// File versions history:
//
// DATE VERSION AUTHOR DESCRIPTION
// - <date> <version> <author> <description>
//
// Language: Verilog 2005
//
// Module Under Test: <Module Name (ModuleName.v)>
//
// Targeted device:
//
// - Vendor: <FPGA manufacturer if vendor specific code>
// - Model: <FPGA Model if model specific>
//
// Description:
//
// <Brief description of the test bench.>
//
//============================================================================================\\
//############################################################################################\\
//============================================================================================\\
`timescale 1ns/100ps
module ModuleName_tb;
//======================================= Declarations =====================================\\
//==== Local parameters ====\\
localparam c_MyParam = 16'hcaca,
c_YourParam = 16'ac1d;
//==== Wires & Regs ====\\
reg Reset_rq;
reg Clk125MHz_kq;
reg ControlReg1_q;
wire StatusWire;
reg [7:0] MyCounter_cb8;
//===================================== Status & Control ====================================\\
//==== Clocks generation ====\\
always #4 Clk125MHz_kq = ~Clk125MHz_kq; // Comment: 8ns period