Commit f6d6e323 authored by Dimitris Lampridis's avatar Dimitris Lampridis
Browse files

[WR-dev] implemented SFP I2C adapter for the VFC-HD board. Tested with hard-coded values, works

parent 45f20a6f
general-cores @ b2d2209d
Subproject commit 4f216443aea2e4a50223c7b72cd02bbbef5bf7c9
Subproject commit b2d2209d3b216a443e778e48b068584d336078d9
......@@ -425,6 +425,8 @@ i_I2cIoExpAndMux (
.dac_sclk_o (PllDacSclk_ok),
.sfp_tx_o (EthSfpTx_o),
.sfp_rx_i (EthSfpRx_i),
.sfp_det_valid_i (1'b1),
.sfp_data_i (128'h415847452d313235342d303533312020),
.eeprom_sda_b (WrPromSda_io),
.eeprom_scl_o (WrPromScl_ok),
.onewire_i (WrOwrIn),
......
wr-cores @ 1a128dc4
Subproject commit fd220473419e2f5b64b1039fb831050692cb77a6
Subproject commit 1a128dc43d54bacd130b65f5762b81cb756ac4b3
......@@ -1978,6 +1978,17 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_PIPELINE=
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_COUNTER_PIPELINE=0" -section_id WbClockDomain
set_global_assignment -name SEARCH_PATH ../../../FpgaModules/SystemSpecific/WhiteRabbit/
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_sync_register.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/altera/gc_shiftreg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_glitch_filt.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_i2c_slave.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/board/vfchd/sfp_i2c_adapter.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/board/wr_board_pkg.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/board/vfchd/xwrc_board_vfchd.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/WhiteRabbit/wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd"
......@@ -2012,9 +2023,6 @@ set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/gener
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd"
set_global_assignment -name VERILOG_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_crc_gen.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/generic_shiftreg_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/altera/generic_sync_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/altera/gc_shiftreg.vhd"
set_global_assignment -name VERILOG_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd"
......@@ -2094,7 +2102,6 @@ set_global_assignment -name VHDL_FILE "../../../FpgaModules/SystemSpecific/White
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_pulse_synchronizer.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/common/gc_extend_pulse.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/genrams/altera/generic_async_fifo.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
set_global_assignment -name VHDL_FILE "../../../FpgaModules/GeneralPurpose/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
......
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