Commit f8a49413 authored by Andrea Boccardi's avatar Andrea Boccardi
Browse files

- I2CSlave made silent (was polluting the simulation display)

- Fixed bugs in the I2cMuxAndExpMaster and its testbench
parent 0893095e
......@@ -191,7 +191,9 @@ generic_fifo_dc_gray #(.dw(11), .aw(4))
.dout(FifoDout_b11),
.re(FifoRead),
.full(FifoFull_o),
.empty(FifoEmpty_o));
.empty(FifoEmpty_o),
.wr_level(/*Not connected*/),
.rd_level(/*Not connected*/));
//==== State Machine ====\\
always @(posedge Clk_ik) State_qb4 <= #1 Rst_irq ? s_Idle : NextState_ab4;
......@@ -229,9 +231,7 @@ always @* begin
end
always @(posedge Clk_ik) begin
// Default assignments
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
// Default assignments
FifoRead <= #1 1'b0;
NewByteRead_op <= #1 1'b0;
AckError_op <= #1 1'b0;
......@@ -265,9 +265,13 @@ always @(posedge Clk_ik) begin
I2cEnChOn_oq <= #1 1'b0;
I2cMuxRdIntOn_oq <= #1 1'b0;
FifoAccessOn_oq <= #1 1'b0;
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
end else case(State_qb4)
// Waiting for a request
s_Idle : begin
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
CommandPointer_c4 <= #1 4'h0;
if (NextState_ab4 != s_Idle) begin
Busy_o <= #1 1'b1;
......
......@@ -89,6 +89,13 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
VmeBusModule
} {} {}} ../../../../../Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module tb_I2cMuxAndExpMaster
Top level modules:
tb_I2cMuxAndExpMaster
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module Generic4InputRegs
......@@ -103,12 +110,12 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
generic_dpram
} {} {}} ../../../../../Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
} {} {}} ../../../../../Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module tb_I2cMuxAndExpMaster
-- Compiling module I2cExpAndMuxMaster
Top level modules:
tb_I2cMuxAndExpMaster
I2cExpAndMuxMaster
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -138,19 +145,19 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
si57x
} {} {}} ../../../../../Hdl/Simulation/Models/pca9534.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9534.v
} {} {}} ../../../../../Hdl/Simulation/Models/I2CSlave.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module pca9534
-- Compiling module I2CSlave
Top level modules:
pca9534
I2CSlave
} {} {}} ../../../../../Hdl/Simulation/Models/I2CSlave.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
} {} {}} ../../../../../Hdl/Simulation/Models/pca9534.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9534.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CSlave
-- Compiling module pca9534
Top level modules:
I2CSlave
pca9534
} {} {}} ../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -166,6 +173,13 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
tb_I2cMuxAndExpMaster
} {} {}} ../../../../../Hdl/Simulation/Models/pca9544a.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module pca9544a
Top level modules:
pca9544a
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CMasterNoBus
......@@ -187,13 +201,6 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
I2cExpAndMuxMaster
} {} {}} ../../../../../Hdl/Simulation/Models/pca9544a.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module pca9544a
Top level modules:
pca9544a
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CMaster
......
......@@ -1744,13 +1744,13 @@ Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_i
Project_File_10 = ../../../../../Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_branch 0 folder VmeInterface vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = ../../../../../Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1455121864 vlog_noload 0 cover_branch 0 folder TestBench vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1455301757 folder TestBench cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_branch 0 folder Ip_OpenCores vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = ../../../../../Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder SystemSpecific last_compile 1455122748 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder SystemSpecific last_compile 1455302005 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = ../../../../../Hdl/Simulation/Models/ivt3205c25mhz.v
......@@ -1760,9 +1760,9 @@ Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 c
Project_File_18 = ../../../../../Hdl/Simulation/Models/si57x.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1403169690 folder Models cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_19 = ../../../../../Hdl/Simulation/Models/I2CSlave.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder Models last_compile 1455122020 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1455301486 folder Models cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_20 = ../../../../../Hdl/Simulation/Models/pca9534.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder Models last_compile 1454949353 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 27 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder Models last_compile 1455299289 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 27 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = ../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder SystemSpecific cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v
......@@ -1770,7 +1770,7 @@ Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 c
Project_File_23 = ../../../../../Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_24 = ../../../../../Hdl/Simulation/Models/pca9544a.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder Models last_compile 1454950650 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder Models last_compile 1455299301 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_25 = ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_26 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v
......
......@@ -4,7 +4,6 @@ K3
cModel Technology
Z0 dE:\VFC-HD\Hdl\Simulation\I2cMuxAndExpMaster\modelsim\project
vAddrDecoderWBApp
!s100 ?A;M5j=GI89QIUbcI=n@W3
IVgel<CkX:d6:^GU@A=>UJ0
VNCHQ_2BBOhhbdo]UGLi?l3
Z1 dE:\VFC-HD\Hdl\Simulation\I2cMuxAndExpMaster\modelsim\project
......@@ -15,15 +14,15 @@ L0 3
Z2 OL;L;10.1c;51
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
Z3 o-work work -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
n@addr@decoder@w@b@app
!s100 ?A;M5j=GI89QIUbcI=n@W3
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
!s108 1455122098.788000
!s107 ../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
!i10b 1
!s85 0
vAddrDecoderWBSys
!s100 I]<o`1gZQhWYfSlV[CcFD1
IT<7[gQF9D^ccocKAN<WZo3
VY2b5ndbk^am=lF=kYWn880
R1
......@@ -34,15 +33,15 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
R3
n@addr@decoder@w@b@sys
!s100 I]<o`1gZQhWYfSlV[CcFD1
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
!s108 1455122099.724000
!s107 ../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
!i10b 1
!s85 0
vfmc_test_wrapper
!s100 X`ZM^GS_W]RfLYa^=GKlb2
IUSnRj63al1Nj3619MMMZ91
Vg>RU2Le@E8IbRX:mXA7LE1
R1
......@@ -53,14 +52,14 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
R3
!s100 X`ZM^GS_W]RfLYa^=GKlb2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
!s108 1455122098.632000
!s107 ../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
!i10b 1
!s85 0
vGeneric4InputRegs
!s100 84A<oA2KUTRdOC2nIRXWJ3
IBcH`gWeR<N5AahH@nVd8_1
VBJA?>jnN3?[mkSzj;L7IQ0
R1
......@@ -71,15 +70,15 @@ L0 1
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
R3
n@generic4@input@regs
!s100 84A<oA2KUTRdOC2nIRXWJ3
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
!s108 1455122099.193000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
!i10b 1
!s85 0
vGeneric4OutputRegs
!s100 AjVMZol<MTb0>VBX9c[;F2
IhI3<ZMz7[fG@GBZ1HUmlE2
V2EW5>JbePYFGgXH_@NUPV1
R1
......@@ -90,15 +89,15 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
R3
n@generic4@output@regs
!s100 AjVMZol<MTb0>VBX9c[;F2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
!s108 1455122100.160000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
!i10b 1
!s85 0
vgeneric_dpram
!s100 n7l]N_H=Be=e1:7kjSI@I2
IQjReDJhNmil7h9Tf:kzf=2
V>UF0oc]5@82:HAX3FCGIT2
R1
......@@ -109,14 +108,14 @@ L0 107
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
R3
!s100 n7l]N_H=Be=e1:7kjSI@I2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
!s108 1455122099.240000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
!i10b 1
!s85 0
vgeneric_fifo_dc_gray
!s100 HccE=Cn`_@j9ZRmK6ac712
ICF>GNl88I=ODk>GR;CkLz1
VbIQRU0]hnVbl_:e=S0TX03
R1
......@@ -127,8 +126,9 @@ L0 127
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
R3
!s100 HccE=Cn`_@j9ZRmK6ac712
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
!s108 1455122099.911000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
!i10b 1
......@@ -138,22 +138,21 @@ VE0T5GVcQDz[D<VaUTdY?d1
r1
!s85 0
31
I]j2SRN>iN9WE22`>G0a:c3
IXG?O0fWQ]UATE;fV:Kk@12
R1
w1455122748
w1455302005
8E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
FE:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
L0 26
R2
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v|
R3
n@i2c@exp@and@mux@master
!i10b 1
!s100 RNF]P:T`Tb^:M>_:;:3BT0
!s108 1455122750.958000
!s100 cBQRHj_Gl9<WSPW>1jMIc0
!s108 1455302012.699000
!s107 E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v|
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v|
vI2CMaster
!s100 biQ;nOFdj@T[V_HU24fdQ3
ICLW;`1nffMzL]aT;D7V;P1
VT_ICIQ^_M7An1Oo=j:ggR2
R1
......@@ -164,15 +163,15 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v|
R3
n@i2@c@master
!s100 biQ;nOFdj@T[V_HU24fdQ3
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v|
!s108 1455122099.958000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v|
!i10b 1
!s85 0
vI2CMasterNoBus
!s100 [^j53A`c::zkllGPd7FK91
IPcR_J2IZD3NCJXLSK7dKD2
VnIlDj:a>6Xc8E6KKe=k]62
R1
......@@ -183,34 +182,34 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v|
R3
n@i2@c@master@no@bus
!s100 [^j53A`c::zkllGPd7FK91
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v|
!s108 1455122099.864000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v|
!i10b 1
!s85 0
vI2CSlave
IR=;m848aoJ]W`W9LV`8YA3
V4nM]KGL`4Xn^jzn3][dko0
r1
31
Iz;:UEZMFii=;NDGnJ1zib2
R1
w1455122020
8../../../../../Hdl/Simulation/Models/I2CSlave.v
F../../../../../Hdl/Simulation/Models/I2CSlave.v
w1455301486
8E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
FE:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
L0 3
R2
r1
31
R3
n@i2@c@slave
!s100 YkUbDHH]PI]Mc;abC46CP3
!s108 1455122099.614000
!s107 ../../../../../Hdl/Simulation/Models/I2CSlave.v|
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/I2CSlave.v|
!i10b 1
!s100 >znF?0n:1eOT[VL;3meBF2
!s108 1455301522.986000
!s107 E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v|
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v|
!s85 0
!i10b 1
vIir1stOrderLp
!s100 gKCYe6VjdX2e_g6WPK]G52
Ij^n4Q>Z7hDN?_bEc3;V>:3
VoJ24KG;bL7_a[nP02kk^72
R1
......@@ -221,15 +220,15 @@ L0 16
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v|
R3
n@iir1st@order@lp
!s100 gKCYe6VjdX2e_g6WPK]G52
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v|
!s108 1455122099.505000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v|
!i10b 1
!s85 0
vInterruptManagerWb
!s100 hoG0@OHg;=;cCIRDkQ`391
Ii0RJ5X>_dbNeJ9?zf`z<K2
V<S`W[kY1QbdcbB8okAYUk2
R1
......@@ -240,15 +239,15 @@ L0 28
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v|
R3
n@interrupt@manager@wb
!s100 hoG0@OHg;=;cCIRDkQ`391
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v|
!s108 1455122098.990000
!s107 ../../../../../Hdl/FpgaModules/SystemSpecific/VmeInterface/InterruptManagerWb.v|
!i10b 1
!s85 0
vivt3205c25mhz
!s100 <lcEd1IdDkUlYY]B3>6J]1
IIFXeon[TTG9o_6Y]a>I0H2
V0n@IzeVDYY1kQGz2R?>]g3
R1
......@@ -259,14 +258,14 @@ L0 2
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/ivt3205c25mhz.v|
R3
!s100 <lcEd1IdDkUlYY]B3>6J]1
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/ivt3205c25mhz.v|
!s108 1455122099.458000
!s107 ../../../../../Hdl/Simulation/Models/ivt3205c25mhz.v|
!i10b 1
!s85 0
vMAX5483
!s100 >4z8B7kQooi[U6<XNNIL61
ISTmH`^Hehmf130];3:Ucb2
V=4OgDN2:R^_:iD;0B]^Ke2
R1
......@@ -277,51 +276,51 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/MAX5483.v|
R3
n@m@a@x5483
!s100 >4z8B7kQooi[U6<XNNIL61
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/MAX5483.v|
!s108 1455122098.944000
!s107 ../../../../../Hdl/Simulation/Models/MAX5483.v|
!i10b 1
!s85 0
vpca9534
Ia]Ll3GPW1Y`>=^f0M7k@K2
VDN;[TDW?aeMGONLkf[UL_3
V3]]SR0b5dkQ4RIKdOW63E0
r1
31
I=<YC^ScizmXSXASDz]EZZ1
R1
w1454949353
8../../../../../Hdl/Simulation/Models/pca9534.v
F../../../../../Hdl/Simulation/Models/pca9534.v
w1455299289
8E:/VFC-HD/Hdl/Simulation/Models/pca9534.v
FE:/VFC-HD/Hdl/Simulation/Models/pca9534.v
L0 3
R2
r1
31
R3
!s100 BfF]FC?6in7D@K`0d>?;T1
!s108 1455122098.538000
!s107 ../../../../../Hdl/Simulation/Models/pca9534.v|
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/pca9534.v|
!i10b 1
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/Simulation/Models/pca9534.v|
!s100 ln10Fm`U9Ah1[zTa`iESi3
!s108 1455299422.121000
!s107 E:/VFC-HD/Hdl/Simulation/Models/pca9534.v|
!s85 0
!i10b 1
vpca9544a
IHPQ@2N5fX@ZQAJ>z5c_MK0
VC<mQ3iCIg3Vj16DncmAWd2
Vl^1d;58P3D2<VMo7S<mIh1
r1
31
IBcI=gXk1B76[k4TJ`lIZC2
R1
w1454950650
8../../../../../Hdl/Simulation/Models/pca9544a.v
F../../../../../Hdl/Simulation/Models/pca9544a.v
w1455299301
8E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v
FE:/VFC-HD/Hdl/Simulation/Models/pca9544a.v
L0 3
R2
r1
31
R3
!s100 2YVLYm5WZ=K;MFfCie=012
!s108 1455122098.694000
!s107 ../../../../../Hdl/Simulation/Models/pca9544a.v|
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/pca9544a.v|
!i10b 1
!s90 -reportprogress|300|-work|work|-vopt|E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v|
!s100 0jL5W7O^Ye9ITCU0=dR5X0
!s108 1455299427.737000
!s107 E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v|
!s85 0
!i10b 1
vPeriodCounter
!s100 K<3UbZ8ceV^^aEY_Ja1VW3
Im[U2Dm^[TT3;7DZ^WDVig1
Vic]FHj8[_@De=h2[6bYF^3
R1
......@@ -332,15 +331,15 @@ L0 2
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v|
R3
n@period@counter
!s100 K<3UbZ8ceV^^aEY_Ja1VW3
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v|
!s108 1455122098.834000
!s107 ../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/PeriodCounter.v|
!i10b 1
!s85 0
vsi57x
!s100 Yg1MJHPF75VooCa4iT];S1
I[SFJOFOdBZ]kDWMn@4]:40
VYUDH0bI]e=GzWQDh0==UR2
R1
......@@ -351,14 +350,14 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/si57x.v|
R3
!s100 Yg1MJHPF75VooCa4iT];S1
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/si57x.v|
!s108 1455122099.568000
!s107 ../../../../../Hdl/Simulation/Models/si57x.v|
!i10b 1
!s85 0
vsn74vmeh22501
!s100 ^4BQj?W1WE?4:6kVO1mRo2
I<?Hc?;49HHeaTKnzaY@VS0
VVc]S8LJzGeFDFoC32?=jR2
R1
......@@ -369,14 +368,14 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/sn74vmeh22501.v|
R3
!s100 ^4BQj?W1WE?4:6kVO1mRo2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/Simulation/Models/sn74vmeh22501.v|
!s108 1455122099.318000
!s107 ../../../../../Hdl/Simulation/Models/sn74vmeh22501.v|
!i10b 1
!s85 0
vSpiMasterWB
!s100 >7^6S1clkT32DU=o9mH4=2
IS1R7@k9=Hj`f2jJgRif6U0
Vc;RFST:gKiMebM`4ac4V20
R1
......@@ -387,41 +386,40 @@ L0 17
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v|
R3
n@spi@master@w@b
!s100 >7^6S1clkT32DU=o9mH4=2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v|
!s108 1455122099.817000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v|
!i10b 1
!s85 0
vtb_I2cMuxAndExpMaster
Z7 DXx6 sv_std 3 std 0 22 F[19LRNL:5;XmIFh[XOPn1
I]cR<3F42Z^TX:m:z<AdIc1
Vl7]AQelW3PFY2^l_7X;VQ2
!s105 tb_I2cMuxAndExpMaster_sv_unit
r1
31
IFSZLoejGJ:``[X_zFJ1]@0
S1
R1
w1455121864
8../../../../..//Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
F../../../../..//Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
w1455301757
8E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
FE:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
L0 33
R2
r1
31
R3
o-work work -sv -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
ntb_@i2c@mux@and@exp@master
!s100 h_=k]h?X[BT`h6nPUl^zg1
!s108 1455122099.661000
!s107 ../../../../..//Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv|
!s90 -reportprogress|300|-work|work|-novopt|../../../../..//Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv|
!i10b 1
!s105 tb_I2cMuxAndExpMaster_sv_unit
!s90 -reportprogress|300|-work|work|-vopt|-sv|E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv|
!s100 S4<8]h`llA1X@9NnQOn`c0
!s108 1455301808.282000
!s107 E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv|
!s85 0
!i10b 1
vtb_VfcBasicAccess
R7
!s100 S>ZNPF8ZI?kRB:?oa]Ll92
Im>1E`O`:cMSR^Jg:=@g>l3
VRAen2DJzLU?XAYVhAf]0L3
!s105 tb_VfcBasicAccess_sv_unit