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Commit f8a49413 authored by Andrea Boccardi's avatar Andrea Boccardi
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- I2CSlave made silent (was polluting the simulation display) 

- Fixed bugs in the I2cMuxAndExpMaster and its testbench
parent 0893095e
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Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
View file @ f8a49413
......@@ -191,7 +191,9 @@ generic_fifo_dc_gray #(.dw(11), .aw(4))
.dout(FifoDout_b11),
.re(FifoRead),
.full(FifoFull_o),
.empty(FifoEmpty_o));
.empty(FifoEmpty_o),
.wr_level(/*Not connected*/),
.rd_level(/*Not connected*/));
//==== State Machine ====\\
always @(posedge Clk_ik) State_qb4 <= #1 Rst_irq ? s_Idle : NextState_ab4;
......@@ -229,9 +231,7 @@ always @* begin
end
always @(posedge Clk_ik) begin
// Default assignments
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
// Default assignments
FifoRead <= #1 1'b0;
NewByteRead_op <= #1 1'b0;
AckError_op <= #1 1'b0;
......@@ -265,9 +265,13 @@ always @(posedge Clk_ik) begin
I2cEnChOn_oq <= #1 1'b0;
I2cMuxRdIntOn_oq <= #1 1'b0;
FifoAccessOn_oq <= #1 1'b0;
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
end else case(State_qb4)
// Waiting for a request
s_Idle : begin
SclOe_e <= #1 1'b0;
SdaOe_e <= #1 1'b0;
CommandPointer_c4 <= #1 4'h0;
if (NextState_ab4 != s_Idle) begin
Busy_o <= #1 1'b1;
......
Hdl/Simulation/I2cMuxAndExpMaster/modelsim/project/I2cMuxAndExpMaster.cr.mti
View file @ f8a49413
......@@ -89,6 +89,13 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
VmeBusModule
} {} {}} ../../../../../Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module tb_I2cMuxAndExpMaster
Top level modules:
tb_I2cMuxAndExpMaster
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module Generic4InputRegs
......@@ -103,12 +110,12 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
generic_dpram
} {} {}} ../../../../../Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv {1 {vlog -work work -vopt -sv E:/VFC-HD/Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
} {} {}} ../../../../../Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module tb_I2cMuxAndExpMaster
-- Compiling module I2cExpAndMuxMaster
Top level modules:
tb_I2cMuxAndExpMaster
I2cExpAndMuxMaster
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -138,19 +145,19 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
si57x
} {} {}} ../../../../../Hdl/Simulation/Models/pca9534.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9534.v
} {} {}} ../../../../../Hdl/Simulation/Models/I2CSlave.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module pca9534
-- Compiling module I2CSlave
Top level modules:
pca9534
I2CSlave
} {} {}} ../../../../../Hdl/Simulation/Models/I2CSlave.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/I2CSlave.v
} {} {}} ../../../../../Hdl/Simulation/Models/pca9534.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9534.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CSlave
-- Compiling module pca9534
Top level modules:
I2CSlave
pca9534
} {} {}} ../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
......@@ -166,6 +173,13 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
tb_I2cMuxAndExpMaster
} {} {}} ../../../../../Hdl/Simulation/Models/pca9544a.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module pca9544a
Top level modules:
pca9544a
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CMasterNoBus
......@@ -187,13 +201,6 @@ Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
Top level modules:
I2cExpAndMuxMaster
} {} {}} ../../../../../Hdl/Simulation/Models/pca9544a.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/Simulation/Models/pca9544a.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module pca9544a
Top level modules:
pca9544a
} {} {}} ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v {1 {vlog -work work -vopt E:/VFC-HD/Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
-- Compiling module I2CMaster
......
Hdl/Simulation/I2cMuxAndExpMaster/modelsim/project/I2cMuxAndExpMaster.mpf
View file @ f8a49413
......@@ -1744,13 +1744,13 @@ Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_i
Project_File_10 = ../../../../../Hdl/FpgaModules/SystemSpecific/VmeInterface/VmeInterfaceWb.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_branch 0 folder VmeInterface vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = ../../../../../Hdl/Simulation/I2cMuxAndExpMaster/tb_I2cMuxAndExpMaster.sv
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 last_compile 1455121864 vlog_noload 0 cover_branch 0 folder TestBench vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type systemverilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat SV vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1455301757 folder TestBench cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_branch 0 folder Ip_OpenCores vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = ../../../../../Hdl/FpgaModules/SystemSpecific/I2cMuxAndExpMaster.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder SystemSpecific last_compile 1455122748 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder SystemSpecific last_compile 1455302005 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 30 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Iir1stOrderLp.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = ../../../../../Hdl/Simulation/Models/ivt3205c25mhz.v
......@@ -1760,9 +1760,9 @@ Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 c
Project_File_18 = ../../../../../Hdl/Simulation/Models/si57x.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1403169690 folder Models cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_19 = ../../../../../Hdl/Simulation/Models/I2CSlave.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder Models last_compile 1455122020 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1455301486 folder Models cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_20 = ../../../../../Hdl/Simulation/Models/pca9534.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder Models last_compile 1454949353 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 27 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder Models last_compile 1455299289 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 27 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_21 = ../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder SystemSpecific cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_22 = ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMasterNoBus.v
......@@ -1770,7 +1770,7 @@ Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 c
Project_File_23 = ../../../../../Hdl/FpgaModules/GeneralPurpose/SpiMasterWB.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_24 = ../../../../../Hdl/Simulation/Models/pca9544a.v
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder Models last_compile 1454950650 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_24 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder Models last_compile 1455299301 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 28 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_25 = ../../../../../Hdl/FpgaModules/GeneralPurpose/I2CMaster.v
Project_File_P_25 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder GeneralPurpose cover_branch 0 cover_fsm 0 last_compile 1434704401 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_26 = ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v
......
Hdl/Simulation/I2cMuxAndExpMaster/modelsim/project/work/_info
View file @ f8a49413
......@@ -4,7 +4,6 @@ K3
cModel Technology
Z0 dE:\VFC-HD\Hdl\Simulation\I2cMuxAndExpMaster\modelsim\project
vAddrDecoderWBApp
!s100 ?A;M5j=GI89QIUbcI=n@W3
IVgel<CkX:d6:^GU@A=>UJ0
VNCHQ_2BBOhhbdo]UGLi?l3
Z1 dE:\VFC-HD\Hdl\Simulation\I2cMuxAndExpMaster\modelsim\project
......@@ -15,15 +14,15 @@ L0 3
Z2 OL;L;10.1c;51
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
Z3 o-work work -L mtiAvm -L mtiOvm -L mtiUvm -L mtiUPF
n@addr@decoder@w@b@app
!s100 ?A;M5j=GI89QIUbcI=n@W3
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
!s108 1455122098.788000
!s107 ../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/AddrDecoderWbApp.v|
!i10b 1
!s85 0
vAddrDecoderWBSys
!s100 I]<o`1gZQhWYfSlV[CcFD1
IT<7[gQF9D^ccocKAN<WZo3
VY2b5ndbk^am=lF=kYWn880
R1
......@@ -34,15 +33,15 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
R3
n@addr@decoder@w@b@sys
!s100 I]<o`1gZQhWYfSlV[CcFD1
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
!s108 1455122099.724000
!s107 ../../../../../Hdl/FpgaModules/SystemSpecific/AddrDecoderWbSys.v|
!i10b 1
!s85 0
vfmc_test_wrapper
!s100 X`ZM^GS_W]RfLYa^=GKlb2
IUSnRj63al1Nj3619MMMZ91
Vg>RU2Le@E8IbRX:mXA7LE1
R1
......@@ -53,14 +52,14 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
R3
!s100 X`ZM^GS_W]RfLYa^=GKlb2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
!s108 1455122098.632000
!s107 ../../../../../Hdl/FpgaModules/ApplicationSpecific/TestProject/FmcTest/fmc_test_wrapper.v|
!i10b 1
!s85 0
vGeneric4InputRegs
!s100 84A<oA2KUTRdOC2nIRXWJ3
IBcH`gWeR<N5AahH@nVd8_1
VBJA?>jnN3?[mkSzj;L7IQ0
R1
......@@ -71,15 +70,15 @@ L0 1
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
R3
n@generic4@input@regs
!s100 84A<oA2KUTRdOC2nIRXWJ3
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
!s108 1455122099.193000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4InputRegs.v|
!i10b 1
!s85 0
vGeneric4OutputRegs
!s100 AjVMZol<MTb0>VBX9c[;F2
IhI3<ZMz7[fG@GBZ1HUmlE2
V2EW5>JbePYFGgXH_@NUPV1
R1
......@@ -90,15 +89,15 @@ L0 3
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
R3
n@generic4@output@regs
!s100 AjVMZol<MTb0>VBX9c[;F2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
!s108 1455122100.160000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Generic4OutputRegs.v|
!i10b 1
!s85 0
vgeneric_dpram
!s100 n7l]N_H=Be=e1:7kjSI@I2
IQjReDJhNmil7h9Tf:kzf=2
V>UF0oc]5@82:HAX3FCGIT2
R1
......@@ -109,14 +108,14 @@ L0 107
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
R3
!s100 n7l]N_H=Be=e1:7kjSI@I2
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
!s108 1455122099.240000
!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_dpram.v|
!i10b 1
!s85 0
vgeneric_fifo_dc_gray
!s100 HccE=Cn`_@j9ZRmK6ac712
ICF>GNl88I=ODk>GR;CkLz1
VbIQRU0]hnVbl_:e=S0TX03
R1
......@@ -127,8 +126,9 @@ L0 127
R2
r1
31
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
R3
!s100 HccE=Cn`_@j9ZRmK6ac712
!s90 -reportprogress|300|-work|work|-novopt|../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
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!s107 ../../../../../Hdl/FpgaModules/GeneralPurpose/Ip_OpenCore/generic_fifo_dc_gray.v|
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......@@ -138,22 +138,21 @@ VE0T5GVcQDz[D<VaUTdY?d1
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n@i2c@exp@and@mux@master
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n@i2@c@master@no@bus
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......@@ -240,15 +239,15 @@ L0 28
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n@interrupt@manager@wb
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......@@ -259,14 +258,14 @@ L0 2
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......@@ -277,51 +276,51 @@ L0 3
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n@m@a@x5483
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......@@ -332,15 +331,15 @@ L0 2
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......@@ -351,14 +350,14 @@ L0 3
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......@@ -369,14 +368,14 @@ L0 3
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......@@ -387,41 +386,40 @@ L0 17
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vtb_I2cMuxAndExpMaster
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