GitLab

The connection is multiplexed with the existing OneWire master. WR PTP core has priority. In order to achieve this, the existing OneWire master interface was slightly modified to provide separately the OneWire inputs and DriverEnable signals.

Sw/Python: fixed bug in I2cIoExpWriteByte() which caused it to stall while waiting for the status of the wrong peripheral

The Bvalue is received as signed encoded in two's complement. the board used
by Patric expects Offset Binary encoding. Thus, conversion is needed.

[WR-dev]: Remove 100MHz clock from default sys_pll, the PHY reconf module of the ArriaV can work with 125MHz as well. Also fix timing constraints after renaming of module instantiations

- Swapped poins of FbClk

- Minor modifications

Updates simulation

I've made few small updates to the VFC-HD repository to both improve its quality and test the GitLab merge-request feature;)

See merge request !1

modified .gitignore for better compatibility; changed BaseProjectSimulation to BaseProject to fit folder scheme

- Added SerDes and related modules
- Added HearBeat module
- Minor cosmetic modifications

[WR-dev] fully merged WR-Btrain, tested with signal-tap, verified correct reception and decoding of Bvalues

TODO: One failed message in timing analyzer, does not seem to affect basic operation