- 13 Oct, 2016 4 commits
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Jan Pospisil authored
modified .gitignore for better compatibility; changed BaseProjectSimulation to BaseProject to fit folder scheme
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Jan Pospisil authored
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Jan Pospisil authored
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Jan Pospisil authored
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- 19 Sep, 2016 2 commits
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Manoel Barros Marin authored
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Manoel Barros Marin authored
- Added SerDes and related modules - Added HearBeat module - Minor cosmetic modifications
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- 14 Sep, 2016 1 commit
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Andrea Boccardi authored
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- 03 Aug, 2016 3 commits
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Manoel Barros Marin authored
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Manoel Barros Marin authored
- External Reset controllers - Fixed bug in TX PLL IP core from Altera - 4x GX operational
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Manoel Barros Marin authored
- Note!!! GBT GX not operational (Reset controller issue) - Dummy Gx operational
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- 18 Jul, 2016 1 commit
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Manoel Barros Marin authored
- Added folder for GBT-FPGA Base project and some related files - Cosmetic modifications
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- 13 Jul, 2016 1 commit
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Manoel Barros Marin authored
- Removed application related methods in Class_VfcHd and renamed Class_VfcHd_System - Added CHILD Class_VfcHd_Base with the applicaction related methods - Adapted Base_Script to the new classes and renamet to Script_Base - Cosmetic modifications to several files
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- 12 Jul, 2016 1 commit
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Manoel Barros Marin authored
- Modified Base application - Fixed reset bug in system - Fixed bug in DpramGenericToWb - Fixed bug in DpramWbToGeneric - Added Generic16InputRegs - Renamed several general purpose and system modules - Reorganiced simulation folders - Removed compiled modules in I2cMuxAndExpMaster (Configuration scripts missing) - Added bitstream and PROM files - Added BaseScript.py - Modified Class_VfcHd - Other minot modifications
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- 30 Apr, 2016 3 commits
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Manoel Barros Marin authored
- Updated simulation test benches accordingly to the previous modification - Modified port name in VmeBus model from Gap_nb5 to Gap_nbm
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Manoel Barros Marin authored
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Manoel Barros Marin authored
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- 28 Apr, 2016 2 commits
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ssh://gitlab.cern.ch:7999/bi/VFC-HDAndrea Boccardi authored
Conflicts: .gitignore Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v
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Andrea Boccardi authored
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- 18 Apr, 2016 3 commits
- 03 Mar, 2016 1 commit
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Manoel Barros Marin authored
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- 02 Mar, 2016 4 commits
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Manoel Barros Marin authored
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Manoel Barros Marin authored
- Fixed issue with Ourput reg in Base project
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Manoel Barros Marin authored
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Manoel Barros Marin authored
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- 01 Mar, 2016 5 commits
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Manoel Barros Marin authored
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Manoel Barros Marin authored
- Modified gitignore
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Manoel Barros Marin authored
- Modified .gitignore
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Manoel Barros Marin authored
-Added FrontEndSpecific folder
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Manoel Barros Marin authored
- Renamed "Ip_OpenCore" to "Ip_OpenCores" - Removed P0BlmIn port from VfcHdTop
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- 25 Feb, 2016 4 commits
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Manoel Barros Marin authored
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Manoel Barros Marin authored
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Manoel Barros Marin authored
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- 24 Feb, 2016 3 commits
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Andrea Boccardi authored
Added 2 documents: the DDR3 parameter explanation from ALTERA (answer from a help request) and the schematic of the board
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Andrea Boccardi authored
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- 23 Feb, 2016 2 commits
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Manoel Barros Marin authored
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Manoel Barros Marin authored
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