modified .gitignore for better compatibility; changed BaseProjectSimulation to BaseProject to fit folder scheme

- Added SerDes and related modules
- Added HearBeat module
- Minor cosmetic modifications

- External Reset controllers
- Fixed bug in TX PLL IP core from Altera
- 4x GX operational

- Note!!! GBT GX not operational (Reset controller issue)
- Dummy Gx operational

- Added folder for GBT-FPGA Base project and some related files
- Cosmetic modifications

- Removed application related methods in Class_VfcHd and renamed Class_VfcHd_System
- Added CHILD Class_VfcHd_Base with the applicaction related methods
- Adapted Base_Script to the new classes and renamet to Script_Base
- Cosmetic modifications to several files

- Modified Base application
- Fixed reset bug in system
- Fixed bug in DpramGenericToWb
- Fixed bug in DpramWbToGeneric
- Added Generic16InputRegs
- Renamed several general purpose and system modules
- Reorganiced simulation folders
- Removed compiled modules in I2cMuxAndExpMaster (Configuration scripts missing)
- Added bitstream and PROM files
- Added BaseScript.py
- Modified Class_VfcHd
- Other minot modifications

- Updated simulation test benches accordingly to the previous modification
- Modified port name in VmeBus model from Gap_nb5 to Gap_nbm

Conflicts:
	.gitignore
	Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v

- Fixed issue with Ourput reg in Base project

- Modified gitignore

- Modified .gitignore

-Added FrontEndSpecific folder

- Renamed "Ip_OpenCore" to "Ip_OpenCores"
- Removed P0BlmIn port from VfcHdTop

Added 2 documents: the DDR3 parameter explanation from ALTERA (answer from a help request) and the schematic of the board