GitLab

TODO: One failed message in timing analyzer, does not seem to affect basic operation

Tested with the WR PTP core, as well as with the WB I2C master already used in the VFC-HD project. Works with both.

[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] WIP to add WR PTP core, PLLs and PHY into the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] imported wr-cores (v3.0) and general-cores (same commit as the one used in v3.0 of wr-cores) as git submodules

[WR-dev] cleaned up almost all Synthesis, Fitter and TimeQuest warnings on Quartus 15.1 before starting adding new modules

- modified address decoder to add WR-Btrain's WB-register space to the decoder
- added module to top-level with loopback

- Updated simulation test benches accordingly to the previous modification
- Modified port name in VmeBus model from Gap_nb5 to Gap_nbm

Conflicts:
	.gitignore
	Hdl/FpgaModules/SystemSpecific/VfcHdSystem.v

- Fixed issue with Ourput reg in Base project

- Modified gitignore

- Modified .gitignore

-Added FrontEndSpecific folder

- Renamed "Ip_OpenCore" to "Ip_OpenCores"
- Removed P0BlmIn port from VfcHdTop

Added 2 documents: the DDR3 parameter explanation from ALTERA (answer from a help request) and the schematic of the board