GitLab

- Minor modifications

- Added SerDes and related modules
- Added HearBeat module
- Minor cosmetic modifications

TODO: One failed message in timing analyzer, does not seem to affect basic operation

Tested with the WR PTP core, as well as with the WB I2C master already used in the VFC-HD project. Works with both.

- External Reset controllers
- Fixed bug in TX PLL IP core from Altera
- 4x GX operational

- Note!!! GBT GX not operational (Reset controller issue)
- Dummy Gx operational

[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] WIP to add WR PTP core, PLLs and PHY into the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] imported wr-cores (v3.0) and general-cores (same commit as the one used in v3.0 of wr-cores) as git submodules

[WR-dev] cleaned up almost all Synthesis, Fitter and TimeQuest warnings on Quartus 15.1 before starting adding new modules

- Added folder for GBT-FPGA Base project and some related files
- Cosmetic modifications

- Removed application related methods in Class_VfcHd and renamed Class_VfcHd_System
- Added CHILD Class_VfcHd_Base with the applicaction related methods
- Adapted Base_Script to the new classes and renamet to Script_Base
- Cosmetic modifications to several files

- Modified Base application
- Fixed reset bug in system
- Fixed bug in DpramGenericToWb
- Fixed bug in DpramWbToGeneric
- Added Generic16InputRegs
- Renamed several general purpose and system modules
- Reorganiced simulation folders
- Removed compiled modules in I2cMuxAndExpMaster (Configuration scripts missing)
- Added bitstream and PROM files
- Added BaseScript.py
- Modified Class_VfcHd
- Other minot modifications

- Updated simulation test benches accordingly to the previous modification
- Modified port name in VmeBus model from Gap_nb5 to Gap_nbm

- Fixed issue with Ourput reg in Base project

- Modified .gitignore

- Renamed "Ip_OpenCore" to "Ip_OpenCores"
- Removed P0BlmIn port from VfcHdTop

- Modified generic I/O registers
- Fixed VME module simulation bugs
- Renamed TestProject to BoardTest folder

- Fixed bugs in the I2cMuxAndExpMaster and its testbench