GitLab

[WR-dev]: Remove 100MHz clock from default sys_pll, the PHY reconf module of the ArriaV can work with 125MHz as well. Also fix timing constraints after renaming of module instantiations

TODO: One failed message in timing analyzer, does not seem to affect basic operation

[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] WIP to add WR PTP core, PLLs and PHY into the wrapper. Synthesis and PAR ok, does not meet timing. Not tested