GitLab

The connection is multiplexed with the existing OneWire master. WR PTP core has priority. In order to achieve this, the existing OneWire master interface was slightly modified to provide separately the OneWire inputs and DriverEnable signals.

Sw/Python: fixed bug in I2cIoExpWriteByte() which caused it to stall while waiting for the status of the wrong peripheral

[WR-dev]: Remove 100MHz clock from default sys_pll, the PHY reconf module of the ArriaV can work with 125MHz as well. Also fix timing constraints after renaming of module instantiations

- Swapped poins of FbClk

- Minor modifications

Updates simulation

I've made few small updates to the VFC-HD repository to both improve its quality and test the GitLab merge-request feature;)

See merge request !1

modified .gitignore for better compatibility; changed BaseProjectSimulation to BaseProject to fit folder scheme

- Added SerDes and related modules
- Added HearBeat module
- Minor cosmetic modifications

TODO: One failed message in timing analyzer, does not seem to affect basic operation

Tested with the WR PTP core, as well as with the WB I2C master already used in the VFC-HD project. Works with both.

- External Reset controllers
- Fixed bug in TX PLL IP core from Altera
- 4x GX operational

- Note!!! GBT GX not operational (Reset controller issue)
- Dummy Gx operational

[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] WIP to add WR PTP core, PLLs and PHY into the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] imported wr-cores (v3.0) and general-cores (same commit as the one used in v3.0 of wr-cores) as git submodules

[WR-dev] cleaned up almost all Synthesis, Fitter and TimeQuest warnings on Quartus 15.1 before starting adding new modules