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The connection is multiplexed with the existing OneWire master. WR PTP core has priority. In order to achieve this, the existing OneWire master interface was slightly modified to provide separately the OneWire inputs and DriverEnable signals.

- Minor modifications

TODO: One failed message in timing analyzer, does not seem to affect basic operation

[WR-dev] Added WB slave interface to the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] WIP to add WR PTP core, PLLs and PHY into the wrapper. Synthesis and PAR ok, does not meet timing. Not tested

[WR-dev] cleaned up almost all Synthesis, Fitter and TimeQuest warnings on Quartus 15.1 before starting adding new modules

- Added folder for GBT-FPGA Base project and some related files
- Cosmetic modifications

- Removed application related methods in Class_VfcHd and renamed Class_VfcHd_System
- Added CHILD Class_VfcHd_Base with the applicaction related methods
- Adapted Base_Script to the new classes and renamet to Script_Base
- Cosmetic modifications to several files

- Modified Base application
- Fixed reset bug in system
- Fixed bug in DpramGenericToWb
- Fixed bug in DpramWbToGeneric
- Added Generic16InputRegs
- Renamed several general purpose and system modules
- Reorganiced simulation folders
- Removed compiled modules in I2cMuxAndExpMaster (Configuration scripts missing)
- Added bitstream and PROM files
- Added BaseScript.py
- Modified Class_VfcHd
- Other minot modifications

- Updated simulation test benches accordingly to the previous modification
- Modified port name in VmeBus model from Gap_nb5 to Gap_nbm

- Fixed issue with Ourput reg in Base project