Commits · c81f7678539de954cb22ed23178fbe9596214693 · Dimitris Lampridis / VFC-HD · GitLab

19 Sep, 2016 1 commit

- Fixed bug in FIFO IP Core · ce495aea

Manoel Barros Marin authored Sep 19, 2016

- Added SerDes and related modules
- Added HearBeat module
- Minor cosmetic modifications

ce495aea

03 Aug, 2016 3 commits
- - GBT-FPGA example with 4 GBT Link Standard Mode fully operational · 0b2e0dce
  Manoel Barros Marin authored Aug 03, 2016
  
  0b2e0dce
- - Upgraded to Quartus Prime 16 · 839efd62
  Manoel Barros Marin authored Aug 03, 2016
```
- External Reset controllers
- Fixed bug in TX PLL IP core from Altera
- 4x GX operational
```
  839efd62
- - GBT-FPGA in application ready · 204202a5
  Manoel Barros Marin authored Aug 03, 2016
```
- Note!!! GBT GX not operational (Reset controller issue)
- Dummy Gx operational
```
  204202a5