/*
  Register definitions for slave core: Simple Wishbone UART

  * File           : wb_uart.h
  * Author         : auto-generated by wbgen2 from simple_uart_wb.wb
  * Created        : Thu May  3 17:36:38 2012
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_uart_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB
#define __WBGEN2_REGDEFS_SIMPLE_UART_WB_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Status Register */

/* definitions for field: TX busy in reg: Status Register */
#define UART_SR_TX_BUSY                       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: RX ready in reg: Status Register */
#define UART_SR_RX_RDY                        WBGEN2_GEN_MASK(1, 1)

/* definitions for register: Baudrate control register */

/* definitions for register: Transmit data regsiter */

/* definitions for field: Transmit data in reg: Transmit data regsiter */
#define UART_TDR_TX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
#define UART_TDR_TX_DATA_SHIFT                0
#define UART_TDR_TX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_TDR_TX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for register: Receive data regsiter */

/* definitions for field: Received data in reg: Receive data regsiter */
#define UART_RDR_RX_DATA_MASK                 WBGEN2_GEN_MASK(0, 8)
#define UART_RDR_RX_DATA_SHIFT                0
#define UART_RDR_RX_DATA_W(value)             WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_RDR_RX_DATA_R(reg)               WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for register: Host VUART Tx register */

/* definitions for field: TX Data in reg: Host VUART Tx register */
#define UART_HOST_TDR_DATA_MASK               WBGEN2_GEN_MASK(0, 8)
#define UART_HOST_TDR_DATA_SHIFT              0
#define UART_HOST_TDR_DATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_HOST_TDR_DATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for field: TX Ready in reg: Host VUART Tx register */
#define UART_HOST_TDR_RDY                     WBGEN2_GEN_MASK(8, 1)

/* definitions for register: Host VUART Rx register */

/* definitions for field: RX Data in reg: Host VUART Rx register */
#define UART_HOST_RDR_DATA_MASK               WBGEN2_GEN_MASK(0, 8)
#define UART_HOST_RDR_DATA_SHIFT              0
#define UART_HOST_RDR_DATA_W(value)           WBGEN2_GEN_WRITE(value, 0, 8)
#define UART_HOST_RDR_DATA_R(reg)             WBGEN2_GEN_READ(reg, 0, 8)

/* definitions for field: RX Ready in reg: Host VUART Rx register */
#define UART_HOST_RDR_RDY                     WBGEN2_GEN_MASK(8, 1)

/* definitions for field: RX FIFO Count in reg: Host VUART Rx register */
#define UART_HOST_RDR_COUNT_MASK              WBGEN2_GEN_MASK(9, 16)
#define UART_HOST_RDR_COUNT_SHIFT             9
#define UART_HOST_RDR_COUNT_W(value)          WBGEN2_GEN_WRITE(value, 9, 16)
#define UART_HOST_RDR_COUNT_R(reg)            WBGEN2_GEN_READ(reg, 9, 16)

#define UART_REG_SR 0x0
#define UART_REG_HOST_TDR 0x10
#define UART_REG_HOST_RDR 0x14

#endif