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This project is for doing more detail simulation for New_MDT_TDC ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
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Firmware dedicated to the communication with the GBTx ASIC
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A new time-to-digital converter (TDC) ASIC prototype is required for the ATLAS Monitored Drift Tube (MDT) detector. This the logic part of this ASIC with TMR. The reference version without TMR is ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
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This repository contains schemes, digital design and documentation of the new MCOI platform, which using Enclustra XU5 module with FPGA ZYNQ (XCZU4EV-SFVC784)
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Firmware dedicated to the communication with the GBTx ASIC
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HDLC for GBT-SCA communication part of DCS work in CRU project.
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This project contains Si5341 internal PLL programming for 240 MHz generation on Reflex Arria10 Board
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Yanliang Han / PLACET
GNU General Public License v2.0 or laterProgram for Linear Accelerator Correction and Efficiency Tests
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Christos Bakalis / gbt-fpga_vc709
GNU General Public License v3.0 onlyGBT-FPGA Implementation on a Xilinx VC709 Evaluation Board
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The implementation of Linear-Regression algorithm from CMSSW to HLS in ten branches and step-wise fashion.
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For testing the frequency of Arria 10 Development board
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Christos Bakalis / sca-extension
GNU General Public License v3.0 onlyThe SCA eXtension (SCAX) is a module designed in order for the users to have full control over the configuration registers of FPGA-based systems in the ATLAS NSW via FELIX.
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