Explore projects
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HPTD / tx_phase_aligner
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTransmitter phase aligner for Xilinx transceivers
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Ales Svetek / surf
Lawrence Berkeley National Labs BSD variant licenseSLAC Ultimate RTL Framework
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Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software
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Ali Skaf / bdaq53
BSD 3-Clause "New" or "Revised" LicenseDAQ and test system for the RD53 readout chips
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As much of the obdt functionality we can develop using the polarfire evaluation board.
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cloned from BE-BI/VFC-HD, with public access and WhiteRabbit additions
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Adrian Fiergolski / HDLVerificationLibrary
GNU General Public License v3.0 onlyIt contains libraries common for HDL verification.
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The second implementation of CBC3 backend firmware and the software interface. Intended to be optimized for wafer testing system.
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HW IP core for controlling the pulser on the CaR board over an AXI bus
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Kade Gigliotti / vmm_boards_firmware
GNU General Public License v3.0 onlyFirmware used for the readout and configuration of the VMM ASIC, a special chip tailored for the needs of ATLAS NSW upgrade.
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Rebecca Louise Ramjiawan / font5-firmware
GNU General Public License v3.0 onlyHDL source code for the FONT5 digital signal processing board
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tmrg / vpisee
GNU General Public License v3.0 onlyA description of how to inject Single Event Effecsts (= Single Event Upsets + Single Event Transient) in a synthesized/place&route netlist using vpi_c functions
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