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Firmware dedicated to the communication with the GBTx ASIC
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Weimin Song / YARR
GNU General Public License v2.0 or laterYet Another Rapid Readout
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This repository contains schemes, digital design and documentation of the new MCOI platform, which using Enclustra XU5 module with FPGA ZYNQ (XCZU4EV-SFVC784)
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Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado
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GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)
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This repository contains necessary files to test Linear-Regression High-Level Synthesis implementation.
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HDLC for GBT-SCA communication part of DCS work in CRU project.
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This project contains Si5341 internal PLL programming for 240 MHz generation on Reflex Arria10 Board
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