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A new time-to-digital converter (TDC) ASIC prototype is required for the ATLAS Monitored Drift Tube (MDT) detector. This the logic part of this ASIC with TMR. The reference version without TMR is ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git

This project is for doing more detail simulation for New_MDT_TDC ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git

This repository contains schemes, digital design and documentation of the new MCOI platform, which using Enclustra XU5 module with FPGA ZYNQ (XCZU4EV-SFVC784)

See https://github.com/scipp-atlas/mario-mapyde

The implementation of Linear-Regression algorithm from CMSSW to HLS in ten branches and step-wise fashion.

This repository contains necessary files to test Linear-Regression High-Level Synthesis implementation.

Instantiation of Linear-Regression module in TM Track-Finder extensible firmware framework.

LiteDTU starting from version 1.2

ITk Strips HCCStar Hardware Emulator

Project to teach hdlmake how to use Microsemi Libero SoC v12.x tools. Still under development.

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

GBT-FPGA Implementation on a Xilinx VC709 Evaluation Board

Firmware dedicated to the communication with the GBTx ASIC

Firmware dedicated to the communication with the GBTx ASIC

GBT Word clk to frame clk for 6 links