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This repository stores the source files and results related to the FPGA programming with Vivado HLS tool

cloned from BE-BI/VFC-HD, with public access and WhiteRabbit additions

Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.

mirror of https://github.com/UVVM/UVVM.git

Internal mirror for UVVM Framework

Update Vivado version used developing phase-1 firmware to 2020.1 .

Update Vivado version used developing phase-1 firmware to 2020.1 .

Take opencores uart and include parity or 9th data bit.

Transmitter phase aligner for Xilinx transceivers

TTC PON related basic PRBS communication test using custom module for Arria10 to Kintex 7 board to board communication

This project is a forked version of the TTC-PON project, adapted to LHCb's needs of timing and control distribution.