Explore projects

VFC-HD system core

VFC-HD base project

cloned from BE-BI/VFC-HD, with public access and WhiteRabbit additions

Modules for the instantiation of the DDR3 of the VFC-HD board

Update Vivado version used developing phase-1 firmware to 2020.1 .

Transmitter phase aligner for Xilinx transceivers

Triple Modular Redundancy Generator

Triple Modular Redundancy Generator

Triple Modular Redundancy Generator

Tower Builder model in System Verilog for integration into VHDL

Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software

A huge VHDL library for FPGA development