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Tower Builder model in System Verilog for integration into VHDL

Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software

A huge VHDL library for FPGA development

SLAC Ultimate RTL Framework

PXI express FMC Carrier Board (SPEXI7U)

VFC-HD related files of the S-GEFE (L-GEFE + C-GEFE) test project

S-GEFE related files of the S-GEFE (L-GEFE + C-GEFE) test project