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HDL source code for the FONT5 digital signal processing board

The second implementation of CBC3 backend firmware and the software interface. Intended to be optimized for wafer testing system.

Triple Modular Redundancy Generator

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

DAQ and test system for the RD53A readout chip

DAQ and test system for the RD53A readout chip

miniDAQ for phase 2 upgrade

This project facilitates the passage and storage of data from a workstation to an external DDR3 memory device on a Stratix 10 GX FPGA board

This repository stores the source files and results related to the FPGA programming with Vivado HLS tool

Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software

Firmware for PCIe cards which run with YARR sw.