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This project facilitates the passage and storage of data from a workstation to an external DDR3 memory device on a Stratix 10 GX FPGA board

Old copy of https://ohwr.org/project/svec. That git repository has been rewritten to remove all PCB stuff (it is on EDMS) and to add HDL and software

Firmware for PCIe cards which run with YARR sw.

SLAC Ultimate RTL Framework

Development of the MGT module for the lpGBT protocol for use in a stratix 10 FPGA (L or H tile)

FMC nanoFIP test HDL for SPEC

DAQ and test system for the RD53A readout chip