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Sources, scripts and generated ip-cores. https://github.com/fpgasystems/davos https://github.com/fpgasystems/fpga-network-stack/

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

Forked repo of the fpga-network-stack https://github.com/fpgasystems/fpga-network-stack

A port of Cyclone-V-ADC-UART to the LASP framework

DAQ and test system for the RD53 readout chips

Firmware dedicated to the communication with the GBTx ASIC

GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)

HDL on Git

An example design for the CMS community which shows the usage of the SLINK sender core. It also contains a core for an SLINK receiver. (This can be used by others but it contains specific elements used in the CMD firmware eco-system)

Update Vivado version used developing phase-1 firmware to 2020.1 .

HDL on Git