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DAQ and test system for the RD53A readout chip

Multi-channel GBT-FPGA core used in FELIX.

Optimized GBT-FPGA : single channel example on KC705.

Project containing design files for my experimentation with the GBT link

DAQ and test system for the RD53A readout chip

Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.

cloned from BE-BI/VFC-HD, with public access and WhiteRabbit additions

Optimized GBT-FPGA : single channel and multi-channel examples on VC709