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Flavio Pisani / ib_flit_sim
Affero General Public License v1.0Fork of the ib_flit_sim project by Mellanox
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A simple piece of VHDL that will generate some 8b10b encoded packages for the HGTD altiroc emulator https://gitlab.cern.ch/atlas-hgtd/hgtd-peb/-/blob/master/Demonstration/module%20emulator%20v2/module_emulator_v2.pdf
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Kai Chen / GBT_KC705
GNU General Public License v3.0 onlyOptimized GBT-FPGA : single channel example on KC705.
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HPTD / tx_phase_aligner
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTransmitter phase aligner for Xilinx transceivers
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The MoCo board is in charge of monitoring and control of the OBDT board. It runs on TM7 hw, in a microTCA crate.
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An example design for the CMS community which shows the usage of the SLINK sender core. It also contains a core for an SLINK receiver. (This can be used by others but it contains specific elements used in the CMD firmware eco-system)
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Developed for 2021 INFIERI school in Madrid
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Jeroen Hegeman / tclink
CERN Open Hardware Licence Version 2 - Weakly ReciprocalTiming Compensated Link
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LHCb / delphes-srcs
Creative Commons Attribution Share Alike 4.0 InternationalUpdated -
Kai Chen / GBT4FELIX
GNU General Public License v3.0 onlyMulti-channel GBT-FPGA core used in FELIX.
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Sioni Paris Summers / conifer
Apache License 2.0Fast inference of Boosted Decision Trees in FPGAs
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