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Firmware for the na62 first level trigger. It works on a Terasic DE4 board with 8 ethernet connections, 4 of them hosted in two HSMC mezzanines. All the details are described in https://twiki.cern.ch/twiki/bin/viewauth/NA62/TDAQL0tp
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GBT-SC for FPGA: This module (VHDL) allows performing slow-control of the front-end through GBT links (GBTx and SCA configuration)
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Basic pin-out build to check pin-planning and ADC clocking structures
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This repository contains necessary files to test Linear-Regression High-Level Synthesis implementation.
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Instantiation of Linear-Regression module in TM Track-Finder extensible firmware framework.
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This repository contains schemes, digital design and documentation of the new MCOI platform, which using Enclustra XU5 module with FPGA ZYNQ (XCZU4EV-SFVC784)
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DAQ supervisory board firmware design for VMM/FPGA-bearing boards. It integrates trigger selection logic, a trigger data processing module and busy logic into a single FPGA that connects to multiple front-end nodes.
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