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ADC readout firmware source for KC705 by using I2C and SiTCP.
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DAQ and test system for the RD53A readout chip
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Demonstration on how a DSP block instantiated as System Generator model is simulated differently in System Generator than (once exported as an IP Core) in Vivado
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Project to teach hdlmake how to use Microsemi Libero SoC v12.x tools. Still under development.
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Instantiation of Linear-Regression module in TM Track-Finder extensible firmware framework.
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Firmware for the na62 first level trigger. It works on a Terasic DE4 board with 8 ethernet connections, 4 of them hosted in two HSMC mezzanines. All the details are described in https://twiki.cern.ch/twiki/bin/viewauth/NA62/TDAQL0tp
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This project is for doing more detail simulation for New_MDT_TDC ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
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A new time-to-digital converter (TDC) ASIC prototype is required for the ATLAS Monitored Drift Tube (MDT) detector. This the logic part of this ASIC with TMR. The reference version without TMR is ssh://git@gitlab.cern.ch:7999/yuliang/New_TDC.git
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