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Commit 1a3c03cf authored by Sioni Summers's avatar Sioni Summers
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Improve timing in payload

parent 11b83430
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...@@ -34,10 +34,12 @@ end emp_payload; ...@@ -34,10 +34,12 @@ end emp_payload;
architecture rtl of emp_payload is architecture rtl of emp_payload is
signal X_scaled : std_logic_vector(895 downto 0) := (others => '0'); signal X_scaled : std_logic_vector(895 downto 0) := (others => '0');
signal X_scaled_vld : std_logic := '0'; signal X_scaled_vld : std_logic := '0';
signal y : std_logic_vector(12 downto 0) := (others => '0'); signal X_scaled_delay : std_logic_vector(895 downto 0) := (others => '0');
signal y_vld : std_logic := '0'; signal X_scaled_vld_delay : std_logic := '0';
signal y : std_logic_vector(12 downto 0) := (others => '0');
signal y_vld : std_logic := '0';
begin begin
...@@ -50,12 +52,16 @@ begin ...@@ -50,12 +52,16 @@ begin
X_vld => X_scaled_vld X_vld => X_scaled_vld
); );
-- add a buffer between the scaler and NN to ease timing
X_scaled_delay <= X_scaled when rising_edge(clk);
X_scaled_vld_delay <= X_scaled_vld when rising_edge(clk);
-- run the NN -- run the NN
NNInstance : entity work.NNWrapper NNInstance : entity work.NNWrapper
port map( port map(
clk => clk_p, clk => clk_p,
X_scaled => X_scaled, X_scaled => X_scaled_delay,
X_vld => X_scaled_vld, X_vld => X_scaled_vld_delay,
y => y, y => y,
y_vld => y_vld y_vld => y_vld
); );
......
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