From 1a3c03cf152ae5b2c1fc4e9df1326265cef3d6fd Mon Sep 17 00:00:00 2001
From: Sioni Summers <14807534+thesps@users.noreply.github.com>
Date: Fri, 8 Dec 2023 10:56:15 +0100
Subject: [PATCH] Improve timing in payload
---
.../firmware/payload/firmware/hdl/payload.vhd | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/part3/firmware/payload/firmware/hdl/payload.vhd b/part3/firmware/payload/firmware/hdl/payload.vhd
index caa4a78..ff9db1d 100644
--- a/part3/firmware/payload/firmware/hdl/payload.vhd
+++ b/part3/firmware/payload/firmware/hdl/payload.vhd
@@ -34,10 +34,12 @@ end emp_payload;
architecture rtl of emp_payload is
- signal X_scaled : std_logic_vector(895 downto 0) := (others => '0');
- signal X_scaled_vld : std_logic := '0';
- signal y : std_logic_vector(12 downto 0) := (others => '0');
- signal y_vld : std_logic := '0';
+ signal X_scaled : std_logic_vector(895 downto 0) := (others => '0');
+ signal X_scaled_vld : std_logic := '0';
+ signal X_scaled_delay : std_logic_vector(895 downto 0) := (others => '0');
+ signal X_scaled_vld_delay : std_logic := '0';
+ signal y : std_logic_vector(12 downto 0) := (others => '0');
+ signal y_vld : std_logic := '0';
begin
@@ -50,12 +52,16 @@ begin
X_vld => X_scaled_vld
);
+ -- add a buffer between the scaler and NN to ease timing
+ X_scaled_delay <= X_scaled when rising_edge(clk);
+ X_scaled_vld_delay <= X_scaled_vld when rising_edge(clk);
+
-- run the NN
NNInstance : entity work.NNWrapper
port map(
clk => clk_p,
- X_scaled => X_scaled,
- X_vld => X_scaled_vld,
+ X_scaled => X_scaled_delay,
+ X_vld => X_scaled_vld_delay,
y => y,
y_vld => y_vld
);
--
GitLab