Add a firmware validation section

part3/part3_fw_validation.ipynb

+{
+ "cells": [
+  {
+   "cell_type": "markdown",
+   "id": "49e7d9d8",
+   "metadata": {},
+   "source": [
+    "# Firmware validation\n",
+    "\n",
+    "Using the pattern files from the CMSSW emulator and the FPGA simulation we can validate our integration.\n",
+    "\n",
+    "Reference files are provided in `solutions/part3/`\n",
+    "- `sink.txt` from the firmware simulation\n",
+    "- `L1TMLDemoPatterns_out_0.txt` from the CMSSW emulator\n",
+    "\n",
+    "We read from the pattern file data to numpy arrays, scaling to the physical range of the data type. Then we plot the distribution and compute the difference between the two."
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "id": "35d206a6",
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "import numpy as np\n",
+    "import matplotlib.pyplot as plt\n",
+    "import os\n",
+    "import mplhep"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "id": "5f5d4181",
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "def read_pattern_file_to_numpy(f):\n",
+    "    '''\n",
+    "    A quick and dirty pattern file reader for our data format\n",
+    "    '''\n",
+    "    fp = open(f)\n",
+    "    lines = fp.readlines()\n",
+    "    X = []\n",
+    "    for line in lines:\n",
+    "        if 'Frame' in line:\n",
+    "            fields = line.split()\n",
+    "            v = '1' in fields[2]\n",
+    "            if v:\n",
+    "                x = int(fields[3], 16)\n",
+    "                x = x / 2**11\n",
+    "                X.append(x)\n",
+    "    return np.array(X, dtype='float')"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "id": "d7cb7022",
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "y_cmssw = read_pattern_file_to_numpy(os.environ['MLATL1T_DIR'] + '/solutions/part3/L1TMLDemoPatterns_out_0.txt')\n",
+    "y_fpga = read_pattern_file_to_numpy(os.environ['MLATL1T_DIR'] + '/solutions/part3/sink.txt')"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "id": "9c0e677b",
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "bins = np.linspace(0, 1, 100)\n",
+    "h_cmssw, _ = np.histogram(y_cmssw, bins=bins)\n",
+    "h_cmssw = h_cmssw.astype('float') / np.sum(h_cmssw)\n",
+    "h_fpga, _ = np.histogram(y_fpga, bins=bins)\n",
+    "h_fpga = h_fpga.astype('float') / np.sum(h_fpga)\n",
+    "mplhep.histplot(h_cmssw, bins, label='CMSSW')\n",
+    "mplhep.histplot(h_fpga, bins, label='FPGA')\n",
+    "plt.xlim((0, 1))\n",
+    "plt.xlabel('y')\n",
+    "plt.semilogy()\n",
+    "plt.legend(loc='upper left')"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "id": "2f099a12",
+   "metadata": {},
+   "outputs": [],
+   "source": [
+    "N = min([len(y_fpga), len(y_cmssw)])\n",
+    "d = y_cmssw[:N] - y_fpga[:N]\n",
+    "bins = np.linspace(-1,1,100)\n",
+    "h, _ = np.histogram(d, bins=bins)\n",
+    "mplhep.histplot(h, bins)\n",
+    "plt.xlim((-1,1))\n",
+    "plt.xlabel('y_cmssw - y_fpga')"
+   ]
+  },
+  {
+   "cell_type": "code",
+   "execution_count": null,
+   "id": "62a005c2",
+   "metadata": {},
+   "outputs": [],
+   "source": []
+  }
+ ],
+ "metadata": {
+  "kernelspec": {
+   "display_name": "Python 3 (ipykernel)",
+   "language": "python",
+   "name": "python3"
+  },
+  "language_info": {
+   "codemirror_mode": {
+    "name": "ipython",
+    "version": 3
+   },
+   "file_extension": ".py",
+   "mimetype": "text/x-python",
+   "name": "python",
+   "nbconvert_exporter": "python",
+   "pygments_lexer": "ipython3",
+   "version": "3.9.14"
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+ },
+ "nbformat": 4,
+ "nbformat_minor": 5
+}