Commit fab71e1b authored by Georg Auzinger's avatar Georg Auzinger
Browse files

merged simplified FW interfaces from branch experimental into Dev

parents bd8838d0 86d9af79
......@@ -9,10 +9,7 @@
*/
//------------------------------------------------------------------------------
//uHal Connection File
// #define UHAL_CONNECTION_FILE "file://settings/connections.xml"
//-----------------------------------------------------------------------------
//Glib Config Files
......@@ -21,266 +18,6 @@
#define XML_DESCRIPTION_FILE_8CBC "settings/HWDescription_8CBC.xml"
#define XML_DESCRIPTION_FILE_16CBC "settings/Beamtest_Nov15.xml"
//------------------------------------------------------------------------------
//Cbc Config Files
// #define DEFAULT_FILE "settings/default_file_Hole.txt"
// #define FE0CBC0HOLE "settings/FE0CBC0Hole.txt"
// #define FE0CBC1 "settings/FE0CBC1.txt"
// #define FE0CBC1HOLE "settings/FE0CBC1Hole.txt"
//---------------REGISTERS------------------------------------------------------
//------------------------------------------------------------------------------
//I2C Parameters
#define I2C_CTRL_ENABLE 0x000009F4
#define I2C_CTRL_DISABLE 0
#define I2C_STROBE 1
#define I2C_M16B 0
#define I2C_MEM 1
#define I2C_WRITE_ADDR 0x09
#define I2C_READ_ADDR 0x06
#define I2C_SLAVE 0x5B
#define I2C_COMMAND "user_wb_ttc_fmc_regs.cbc_reg_i2c_command"
#define I2C_REPLY "user_wb_ttc_fmc_regs.cbc_reg_i2c_reply"
#define I2C_SETTINGS "user_wb_ttc_fmc_regs.cbc_reg_i2c_settings"
#define MAX_NB_LOOP 70
//------------------------------------------------------------------------------
//Board infos
#define BOARD_TYPE "board_id"
#define FW_VERSION_MAJOR "firm_id.firmware_major"
#define FW_VERSION_MINOR "firm_id.firmware_minor"
#define FW_VERSION_BUILD "firm_id.firmware_build"
#define FMC1_PRESENT "status.fmc1_present"
#define FMC2_PRESENT "status.fmc2_present"
// User FW infos
//FMC infos
#define FMC_USER_BOARD_ID "user_wb_ttc_fmc_regs.user_board_id"
#define FMC_USER_SYS_ID "user_wb_ttc_fmc_regs.user_sys_id"
#define FMC_USER_VERSION "user_wb_ttc_fmc_regs.user_version"
//------------------------------------------------------------------------------
//GLIB Useful Registers
//SRAM
//SRAM IDs
#define SRAM1 "sram1"
#define SRAM2 "sram2"
// needed to avoid IPBUS bug
#define SRAM1_256 "sram1_256"
#define SRAM2_256 "sram2_256"
//SRAM user logic
#define SRAM1_USR_LOGIC "ctrl_sram.sram1_user_logic"
#define SRAM2_USR_LOGIC "ctrl_sram.sram2_user_logic"
//SRAM End Readout
#define SRAM1_END_READOUT "user_wb_ttc_fmc_regs.pc_commands.SRAM1_end_readout"
#define SRAM2_END_READOUT "user_wb_ttc_fmc_regs.pc_commands.SRAM2_end_readout"
//SRAM Full flags, reset when their end readout is 1
#define SRAM1_FULL "user_wb_ttc_fmc_regs.flags.SRAM1_full"
#define SRAM2_FULL "user_wb_ttc_fmc_regs.flags.SRAM2_full"
//GLIB
//GLIBS settings
#define FAKE_DATA "user_wb_ttc_fmc_regs.pc_commands.CBC_DATA_GENE"
#define EXT_TRG "user_wb_ttc_fmc_regs.pc_commands.TRIGGER_SEL"
//Hybrid
#define HYBRID_TYPE "hybrid_type"
#define HYBRID_VERSION "user_wb_ttc_fmc_regs.new.hybrid_version"
//NB FE
#define NB_FE "nb_FE"
//------------------------------------------------------------------------------
//CBC
//CBC expectation
#define CBC_EXPECTED "CBC_expected"
//CBC DATA PACKET NUMBER
#define CBC_PACKET_NB "user_wb_ttc_fmc_regs.pc_commands.CBC_DATA_PACKET_NUMBER"
//CBC TEST PULSE VALID
#define CBC_TEST_PULSE_VALID "COMMISSIONNING_MODE_CBC_TEST_PULSE_VALID"
//CBC Data generator
#define CBC_DATA_GENE "user_wb_ttc_fmc_regs.pc_commands.CBC_DATA_GENE"
//CBC_TRIGGER_ONE_SHOT
#define CBC_TRIGGER_1SHOT "user_wb_ttc_fmc_regs.cbc_acquisition.CBC_TRIGGER_ONE_SHOT"
//CBC stubdata latency adjustement
#define CBC_STUB_LATENCY "cbc_stubdata_latency_adjust"
#define CBC_STUB_LATENCY_FE1 "cbc_stubdata_latency_adjust_fe1"
#define CBC_STUB_LATENCY_FE2 "cbc_stubdata_latency_adjust_fe2"
//CBC I2C command acknoledgement
#define CBC_I2C_CMD_ACK "cbc_i2c_cmd_ack"
#define CBC_I2C_CMD_ACK_FE1 "cbc_i2c_cmd_ack_fe1"
#define CBC_I2C_CMD_ACK_FE2 "cbc_i2c_cmd_ack_fe2"
//CBC I2C command request
#define CBC_I2C_CMD_RQ "cbc_i2c_cmd_rq"
#define CBC_I2C_CMD_RQ_FE1 "cbc_i2c_cmd_rq_fe1"
#define CBC_I2C_CMD_RQ_FE2 "cbc_i2c_cmd_rq_fe2"
//CBC Hard Reset
#define CBC_HARD_RESET "cbc_hard_reset"
#define CBC_HARD_RESET_FE1 "cbc_hard_reset_fe1"
#define CBC_HARD_RESET_FE2 "cbc_hard_reset_fe2"
//CBC Fast Reset
#define CBC_FAST_RESET "cbc_fast_reset"
#define CBC_FAST_RESET_FE1 "cbc_fast_reset_fe1"
#define CBC_FAST_RESET_FE2 "cbc_fast_reset_fe2"
//Enable Cbc
//FE0
#define ENABLE_FE0_CBC0 "user_wb_ttc_fmc_regs.FE0.CBC0"
#define ENABLE_FE0_CBC1 "user_wb_ttc_fmc_regs.FE0.CBC1"
#define ENABLE_FE0_CBC2 "user_wb_ttc_fmc_regs.FE0.CBC2"
#define ENABLE_FE0_CBC3 "user_wb_ttc_fmc_regs.FE0.CBC3"
#define ENABLE_FE0_CBC4 "user_wb_ttc_fmc_regs.FE0.CBC4"
#define ENABLE_FE0_CBC5 "user_wb_ttc_fmc_regs.FE0.CBC5"
#define ENABLE_FE0_CBC6 "user_wb_ttc_fmc_regs.FE0.CBC6"
#define ENABLE_FE0_CBC7 "user_wb_ttc_fmc_regs.FE0.CBC7"
#define ENABLE_FE0_CBC8 "user_wb_ttc_fmc_regs.FE0.CBC8"
#define ENABLE_FE0_CBC9 "user_wb_ttc_fmc_regs.FE0.CBC9"
#define ENABLE_FE0_CBC10 "user_wb_ttc_fmc_regs.FE0.CBC10"
#define ENABLE_FE0_CBC11 "user_wb_ttc_fmc_regs.FE0.CBC11"
#define ENABLE_FE0_CBC12 "user_wb_ttc_fmc_regs.FE0.CBC12"
#define ENABLE_FE0_CBC13 "user_wb_ttc_fmc_regs.FE0.CBC13"
#define ENABLE_FE0_CBC14 "user_wb_ttc_fmc_regs.FE0.CBC14"
#define ENABLE_FE0_CBC15 "user_wb_ttc_fmc_regs.FE0.CBC15"
#define CBC_FE0_ENABLED "user_wb_ttc_fmc_regs.FE0.enabled"
//FE1
#define ENABLE_FE1_CBC0 "user_wb_ttc_fmc_regs.FE1.CBC0"
#define ENABLE_FE1_CBC1 "user_wb_ttc_fmc_regs.FE1.CBC1"
#define ENABLE_FE1_CBC2 "user_wb_ttc_fmc_regs.FE1.CBC2"
#define ENABLE_FE1_CBC3 "user_wb_ttc_fmc_regs.FE1.CBC3"
#define ENABLE_FE1_CBC4 "user_wb_ttc_fmc_regs.FE1.CBC4"
#define ENABLE_FE1_CBC5 "user_wb_ttc_fmc_regs.FE1.CBC5"
#define ENABLE_FE1_CBC6 "user_wb_ttc_fmc_regs.FE1.CBC6"
#define ENABLE_FE1_CBC7 "user_wb_ttc_fmc_regs.FE1.CBC7"
#define ENABLE_FE1_CBC8 "user_wb_ttc_fmc_regs.FE1.CBC8"
#define ENABLE_FE1_CBC9 "user_wb_ttc_fmc_regs.FE1.CBC9"
#define ENABLE_FE1_CBC10 "user_wb_ttc_fmc_regs.FE1.CBC10"
#define ENABLE_FE1_CBC11 "user_wb_ttc_fmc_regs.FE1.CBC11"
#define ENABLE_FE1_CBC12 "user_wb_ttc_fmc_regs.FE1.CBC12"
#define ENABLE_FE1_CBC13 "user_wb_ttc_fmc_regs.FE1.CBC13"
#define ENABLE_FE1_CBC14 "user_wb_ttc_fmc_regs.FE1.CBC14"
#define ENABLE_FE1_CBC15 "user_wb_ttc_fmc_regs.FE1.CBC15"
#define CBC_FE1_ENABLED "user_wb_ttc_fmc_regs.FE1.enabled"
//------------------------------------------------------------------------------
//Delays
//Delay after fast reset
#define DELAY_AF_FAST_RESET "COMMISSIONNING_MODE_DELAY_AFTER_FAST_RESET"
//Delay after L1A
#define DELAY_AF_L1A "COMMISSIONNING_MODE_DELAY_AFTER_L1A"
//Delay after test pulse
#define DELAY_AF_TEST_PULSE "COMMISSIONNING_MODE_DELAY_AFTER_TEST_PULSE"
//------------------------------------------------------------------------------
//Triggers
//Break Trigger
#define BREAK_TRIGGER "break_trigger"
//Internal Trigger freq
#define INT_TRIGGER_FREQ "user_wb_ttc_fmc_regs.pc_commands.INT_TRIGGER_FREQ"
//Trigger Select
#define TRIGGER_SELECT "user_wb_ttc_fmc_regs.pc_commands.TRIGGER_SEL"
// Threshold for DIO5
#define TRIGGER_THRESHOLD "user_wb_ttc_fmc_regs.dio5.fmcdio5_threshold_trig_in"
// Trigger Edge
#define TRIGGER_EDGE "user_wb_ttc_fmc_regs.dio5.fmcdio5_trig_in_edge"
//input termination
#define TRIGGER_IN_TERMINATE "user_wb_ttc_fmc_regs.dio5.fmcdio5_trig_in_50ohms"
// Output termination
#define TRIGGER_OUT_TERMINATE "user_wb_ttc_fmc_regs.dio5.fmcdio5_trig_out_50ohms"
// Lemo 2 signal
#define LEMO2_SIGNAL "user_wb_ttc_fmc_regs.dio5.fmcdio5_lemo2_sig_sel"
//------------------------------------------------------------------------------
//Clock
// Clock select
#define CLK_SELECT "user_wb_ttc_fmc_regs.dio5.clk_mux_sel"
// Clock threshold
#define CLK_THRESHOLD "user_wb_ttc_fmc_regs.dio5.fmcdio5_threshold_clk_in"
// Input termination
#define CLK_IN_TERMINATE "user_wb_ttc_fmc_regs.dio5.fmcdio5_clk_in_50ohms"
// Output termination
#define CLK_OUT_TERMINATE "user_wb_ttc_fmc_regs.dio5.fmcdio5_clk_out_50ohms"
//------------------------------------------------------------------------------
//Backpressure
#define BACKPRESSURE_POLARITY "user_wb_ttc_fmc_regs.dio5.fmcdio5_backpressure_out_polar"
//------------------------------------------------------------------------------
//Others
//PC Config OK
#define PC_CONFIG_OK "user_wb_ttc_fmc_regs.pc_commands.PC_config_ok"
//Spurious frame
#define SPURIOUS_FRAME "user_wb_ttc_fmc_regs.pc_commands.SPURIOUS_FRAME"
//Force BG0 Start
#define FORCE_BG0_START "user_wb_ttc_fmc_regs.pc_commands2.force_BG0_start"
//CMD_START_VALID Flag
#define CMD_START_VALID "user_wb_ttc_fmc_regs.status_flags.CMD_START_VALID"
//FE expectation
#define FE_EXPECTED "FE_expected"
//RQ
#define RQ "COMMISSIONNING_MODE_RQ"
// Test Pulse in commissioning mode
#define ENABLE_TP "COMMISSIONNING_MODE_CBC_TEST_PULSE_VALID"
//Acquisition mode
#define ACQ_MODE "user_wb_ttc_fmc_regs.pc_commands.ACQ_MODE"
//Clock shift
#define CLOCK_SHIFT "user_wb_ttc_fmc_regs.pc_commands2.clock_shift"
//Negative logic
#define NEG_LOGIC_CBC "user_wb_ttc_fmc_regs.pc_commands2.negative_logic_CBC"
#define NEG_LOGIC_STTS "user_wb_ttc_fmc_regs.pc_commands2.negative_logic_sTTS"
//Polarity
#define POLARITY_TLU "user_wb_ttc_fmc_regs.pc_commands2.polarity_tlu"
//Time out for stack writing
#define TIME_OUT 5
......@@ -288,6 +25,7 @@
//------------------------------------------------------------------------------
//Events
#define NCHANNELS 254
//in uint32_t words
#define CBC_EVENT_SIZE_32 9 // 9 32bit words per CBC
......
......@@ -101,6 +101,11 @@ void BeBoardFWInterface::EncodeReg( const CbcRegItem& pRegItem, uint8_t pCbcId,
pVecReq.push_back( ( pCbcId >> 3 ) << 21 | ( pCbcId & 7 ) << 17 | pRegItem.fPage << 16 | pRegItem.fAddress << 8 | pRegItem.fValue );
}
void BeBoardFWInterface::EncodeReg( const CbcRegItem& pRegItem, uint8_t pFeId, uint8_t pCbcId, std::vector<uint32_t>& pVecReq )
{
// (pCbcId & 7) restarts CbcIDs from 0 for FE 1 (if CbcID > 7)
pVecReq.push_back( pFeId >> 3 ) << 21 | pCbcId << 17 | pRegItem.fPage << 16 | pRegItem.fAddress << 8 | pRegItem.fValue );
}
void BeBoardFWInterface::DecodeReg( CbcRegItem& pRegItem, uint8_t pCbcId, uint32_t pWord )
{
......
......@@ -111,6 +111,13 @@ public:
*/
virtual void EncodeReg( const CbcRegItem& pRegItem, uint8_t pCbcId, std::vector<uint32_t>& pVecReq ); /*!< Encode a/several word(s) readable for a Cbc*/
/*!
* \brief Encode a/several word(s) readable for a Cbc
* \param pRegItem : RegItem containing infos (name, adress, value...) about the register to write
* \param pCbcId : Id of the Cbc to work with
* \param pVecReq : Vector to stack the encoded words
*/
virtual void EncodeReg( const CbcRegItem& pRegItem, uint8_t pFeId, uint8_t pCbcId, std::vector<uint32_t>& pVecReq ); /*!< Encode a/several word(s) readable for a Cbc*/
/*!
* \brief Decode a word from a read of a register of the Cbc
* \param pRegItem : RegItem containing infos (name, adress, value...) about the register to read
* \param pCbcId : Id of the Cbc to work with
......
This diff is collapsed.
......@@ -31,31 +31,31 @@ using namespace Ph2_HwDescription;
*/
namespace Ph2_HwInterface
{
class CtaFpgaConfig;
class CtaFpgaConfig;
/*!
* \class CtaFWInterface
* \brief init/config of the CTA and its Cbc's
*/
class CtaFWInterface : public BeBoardFWInterface
{
/*!
* \class CtaFWInterface
* \brief init/config of the CTA and its Cbc's
*/
class CtaFWInterface : public BeBoardFWInterface
{
private:
Data* fData; /*!< Data read storage*/
private:
Data* fData; /*!< Data read storage*/
struct timeval fStartVeto;
std::string fStrSram, fStrSramUserLogic, fStrFull, fStrReadout, fStrOtherSram, fStrOtherSramUserLogic;
std::string fCbcStubLat, fCbcI2CCmdAck, fCbcI2CCmdRq, fCbcHardReset, fCbcFastReset;
CtaFpgaConfig* fpgaConfig;
FileHandler* fFileHandler ;
struct timeval fStartVeto;
std::string fStrSram, fStrSramUserLogic, fStrFull, fStrReadout, fStrOtherSram, fStrOtherSramUserLogic;
std::string fCbcStubLat, fCbcI2CCmdAck, fCbcI2CCmdRq, fCbcHardReset, fCbcFastReset;
CtaFpgaConfig* fpgaConfig;
FileHandler* fFileHandler ;
private:
/*!
* \brief SRAM selection for DAQ
* \param pNthAcq : actual number of acquisitions
*/
void SelectDaqSRAM( uint32_t pNthAcq );
private:
/*!
* \brief SRAM selection for DAQ
* \param pNthAcq : actual number of acquisitions
*/
void SelectDaqSRAM( uint32_t pNthAcq );
public:
/*!
......@@ -74,140 +74,136 @@ public:
CtaFWInterface( const char* pId, const char* pUri, const char* pAddressTable );
CtaFWInterface( const char* pId, const char* pUri, const char* pAddressTable, FileHandler* pFileHandler );
/*!
* \brief Destructor of the CtaFWInterface class
*/
~CtaFWInterface() {
if ( fData ) delete fData;
}
/*!
* \brief Configure the board with its Config File
* \param pBoard
*/
void ConfigureBoard( const BeBoard* pBoard ) override;
/*!
* \brief Detect the right FE Id to write the right registers (not working with the latest Firmware)
*/
void SelectFEId();
/*!
* \brief Start a DAQ
*/
void Start() override;
/*!
* \brief Stop a DAQ
* \param pNthAcq : actual number of acquisitions
*/
void Stop( uint32_t pNthAcq ) override;
/*!
* \brief Pause a DAQ
*/
void Pause() override;
/*!
* \brief Unpause a DAQ
*/
void Resume() override;
/*!
* \brief Read data from DAQ
* \param pNthAcq : actual number of acquisitions
* \param pBreakTrigger : if true, enable the break trigger
* \return cNPackets: the number of packets read
*/
uint32_t ReadData( BeBoard* pBoard, uint32_t pNthAcq, bool pBreakTrigger ) override;
/*!
* \brief Get next event from data buffer
* \return Next event
*/
const Event* GetNextEvent( const BeBoard* pBoard ) const override {
return fData->GetNextEvent( pBoard );
}
const Event* GetEvent( const BeBoard* pBoard, int i ) const override {
return fData->GetEvent( pBoard, i );
}
const std::vector<Event*>& GetEvents( const BeBoard* pBoard ) const override {
return fData->GetEvents( pBoard );
}
/*! \brief Read a block of a given size
* \param pRegNode Param Node name
* \param pBlocksize Number of 32-bit words to read
* \return Vector of validated 32-bit values
*/
std::vector<uint32_t> ReadBlockRegValue( const std::string& pRegNode, const uint32_t& pBlocksize ) override;
void StartThread( BeBoard* pBoard, uint32_t uNbAcq, HwInterfaceVisitor* visitor ) override;
//Methods for the Cbc's:
private:
//I2C Methods
/*!
* \brief Wait for the I2C command acknowledgement
* \param pAckVal : Expected status of acknowledgement, 1/0 -> true/false
* \param pNcount : Number of registers at stake
* \return boolean confirming the acknowledgement
*/
bool I2cCmdAckWait( uint32_t pAckVal, uint8_t pNcount = 1 );
/*!
* \brief Send request to r/w blocks via I2C
* \param pVecReq : Block of words to send
* \param pWrite : 1/0 -> Write/Read
*/
void SendBlockCbcI2cRequest( std::vector<uint32_t>& pVecReq, bool pWrite );
/*!
* \brief Read blocks from SRAM via I2C
* \param pVecReq : Vector to stack the read words
*/
void ReadI2cBlockValuesInSRAM( std::vector<uint32_t>& pVecReq );
/*!
* \brief Enable I2C communications
* \param pEnable : 1/0 -> Enable/Disable
*/
void EnableI2c( bool pEnable );
void SelectFeSRAM( uint32_t pFe );
/*! Compute the size of an acquisition data block
* \return Number of 32-bit words to be read at each iteration */
uint32_t computeBlockSize( BeBoard* pBoard );
void checkIfUploading();
public:
//r/w the Cbc registers
/*!
* \brief Read register blocks of a Cbc
* \param pFeId : FrontEnd to work with
* \param pVecReq : Vector to stack the read words
*/
void WriteCbcBlockReg( uint8_t pFeId, std::vector<uint32_t>& pVecReq );
/*! \brief Read register blocks of a Cbc
* \param pFeId : FrontEnd to work with
* \param pVecReq : Vector to stack the read words
*/
void ReadCbcBlockReg( uint8_t pFeId, std::vector<uint32_t>& pVecReq );
/*! \brief Upload a firmware (FPGA configuration) from a file in MCS format into a given configuration
* \param strConfig FPGA configuration name
* \param pstrFile path to MCS file
*/
void FlashProm( const std::string& strConfig, const char* pstrFile );
/*! \brief Jump to an FPGA configuration */
void JumpToFpgaConfig( const std::string& strConfig);
void DownloadFpgaConfig( const std::string& strConfig, const std::string& strDest );
/*! \brief Is the FPGA being configured ?
* \return FPGA configuring process or NULL if configuration occurs */
const FpgaConfig* getConfiguringFpga() {
return (const FpgaConfig*)fpgaConfig;
}
/*! \brief Get the list of available FPGA configuration (or firmware images)*/
std::vector<std::string> getFpgaConfigList( );
/*! \brief Delete one Fpga configuration (or firmware image)*/
void DeleteFpgaConfig( const std::string& strId);
void threadAcquisitionLoop( BeBoard* pBoard, HwInterfaceVisitor* visitor );
};
/*!
* \brief Destructor of the CtaFWInterface class
*/
~CtaFWInterface()
{
if ( fData ) delete fData;
}
/*!
* \brief Configure the board with its Config File
* \param pBoard
*/
void ConfigureBoard( const BeBoard* pBoard ) override;
/*!
* \brief Start a DAQ
*/
void Start() override;
/*!
* \brief Stop a DAQ
* \param pNthAcq : actual number of acquisitions
*/
void Stop( uint32_t pNthAcq ) override;
/*!
* \brief Pause a DAQ
*/
void Pause() override;
/*!
* \brief Unpause a DAQ
*/
void Resume() override;
/*!
* \brief Read data from DAQ
* \param pNthAcq : actual number of acquisitions
* \param pBreakTrigger : if true, enable the break trigger
* \return cNPackets: the number of packets read
*/
uint32_t ReadData( BeBoard* pBoard, uint32_t pNthAcq, bool pBreakTrigger ) override;
/*!
* \brief Get next event from data buffer
* \return Next event
*/
const Event* GetNextEvent( const BeBoard* pBoard ) const override
{
return fData->GetNextEvent( pBoard );
}
const Event* GetEvent( const BeBoard* pBoard, int i ) const override
{
return fData->GetEvent( pBoard, i );
}
const std::vector<Event*>& GetEvents( const BeBoard* pBoard ) const override
{
return fData->GetEvents( pBoard );
}
/*! \brief Read a block of a given size
* \param pRegNode Param Node name
* \param pBlocksize Number of 32-bit words to read
* \return Vector of validated 32-bit values
*/
std::vector<uint32_t> ReadBlockRegValue( const std::string& pRegNode, const uint32_t& pBlocksize ) override;
bool WriteBlockReg( const std::string& pRegNode, const std::vector< uint32_t >& pValues ) override;
void StartThread( BeBoard* pBoard, uint32_t uNbAcq, HwInterfaceVisitor* visitor ) override;
//Methods for the Cbc's:
private:
//I2C Methods
/*!
* \brief Wait for the I2C command acknowledgement
* \param pAckVal : Expected status of acknowledgement, 1/0 -> true/false
* \param pNcount : Number of registers at stake
* \return boolean confirming the acknowledgement
*/
bool I2cCmdAckWait( uint32_t pAckVal, uint8_t pNcount = 1 );
/*!
* \brief Send request to r/w blocks via I2C
* \param pVecReq : Block of words to send
* \param pWrite : 1/0 -> Write/Read
*/
void WriteI2C( std::vector<uint32_t>& pVecReq, bool pWrite );
/*!
* \brief Read blocks from SRAM via I2C
* \param pVecReq : Vector to stack the read words
*/
void ReadI2C( std::vector<uint32_t>& pVecReq );
/*! Compute the size of an acquisition data block
* \return Number of 32-bit words to be read at each iteration */
uint32_t computeBlockSize( BeBoard* pBoard );
void checkIfUploading();
public:
//r/w the Cbc registers
/*!
* \brief Read register blocks of a Cbc
* \param pFeId : FrontEnd to work with
* \param pVecReq : Vector to stack the read words
*/
void WriteCbcBlockReg( uint8_t pFeId, std::vector<uint32_t>& pVecReq );
/*! \brief Read register blocks of a Cbc
* \param pFeId : FrontEnd to work with
* \param pVecReq : Vector to stack the read words
*/
void ReadCbcBlockReg( uint8_t pFeId, std::vector<uint32_t>& pVecReq );
/*! \brief Upload a firmware (FPGA configuration) from a file in MCS format into a given configuration
* \param strConfig FPGA configuration name
* \param pstrFile path to MCS file
*/
void FlashProm( const std::string& strConfig, const char* pstrFile );
/*! \brief Jump to an FPGA configuration */
void JumpToFpgaConfig( const std::string& strConfig);
/*! \brief Is the FPGA being configured ?
* \return FPGA configuring process or NULL if configuration occurs */
const FpgaConfig* getConfiguringFpga()
{
return (const FpgaConfig*)fpgaConfig;
}