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Commit caa96d98 authored by Julian Maxime Mendez's avatar Julian Maxime Mendez
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* Remove LpGBT emulator

* Connect reset to VIO
* Update example with the latest LpGBT-FPGA core version
* Add PRBS Generator / checkers (remove old gen/checker)
parent 15cf0cfc
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1 merge request!1Resolve "Cleaning: move the LpGBT emulator to a dedicated project"
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with 7 additions and 1058 deletions
......@@ -33,25 +33,15 @@ create_clock -period 3.125 -name SMA_MGT_REFCLK [get_ports SMA_MGT_REFCLK_P]
set_property RXSLIDE_MODE PMA [get_cells -hier -filter {NAME =~ *GTHE3_CHANNEL_PRIM_INST}]
set_property LOC GTHE3_CHANNEL_X0Y9 [get_cells -hierarchical -filter {NAME =~ *lpgbtemul_top_inst*gen_channel_container[0].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
set_property LOC GTHE3_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ *lpgbtFpga_top_inst*gen_channel_container[0].*gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
##===================================================================================================##
##===================================================================================================##
##====================##
## TIMING CONSTRAINTS ##
##====================##
# Multicycle constraints
set_multicycle_path 3 -from [get_pins {lpgbtFpga_top_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_pipelined_s_reg[*]/C}] -setup
set_multicycle_path 2 -from [get_pins {lpgbtFpga_top_inst/LpGBT_FPGA_Uplink_datapath_inst/uplinkFrame_pipelined_s_reg[*]/C}] -hold
set_multicycle_path 3 -from [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/LpGBT_FPGA_Uplink_datapath_inst*descrambledData_reg[*]/C}] -setup
set_multicycle_path 2 -from [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/LpGBT_FPGA_Uplink_datapath_inst*descrambledData_reg[*]/C}] -hold
#Debug: no need to constraint the design for debug
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *ila_core_inst*/D}]
#Debug: no need to constraint the design for static signal (status)
set_false_path -to [get_pins uplinkstimulis_top_inst/uplink_error_o_reg/D]
#Ready status: false route - timing is not critical for asynchronous reset (long duration)
set_false_path -from [get_pins lpgbtemul_top_inst/mgt_framealigner_inst/sta_headerLocked_s_reg/C]
set_multicycle_path 5 -from [get_pins {lpgbtemul_top_inst/rxGearbox_inst/dat_outFrame_o_reg[*]/C}] -setup
set_multicycle_path 4 -from [get_pins {lpgbtemul_top_inst/rxGearbox_inst/dat_outFrame_o_reg[*]/C}] -hold
set_multicycle_path 2 -from [get_pins -hierarchical -filter {NAME =~ lpgbtemul_top_inst*LpGBT_Model_dataPath_inst*scrambledData_reg[*]/C}] -setup
set_multicycle_path 1 -from [get_pins -hierarchical -filter {NAME =~ lpgbtemul_top_inst*LpGBT_Model_dataPath_inst*scrambledData_reg[*]/C}] -hold
set_multicycle_path -setup -to [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/LpGBT_FPGA_dataPath_inst/scrambler36bitOrder36_inst/scrambledData*/D}] 3
set_multicycle_path -hold -to [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/LpGBT_FPGA_dataPath_inst/scrambler36bitOrder36_inst/scrambledData*/D}] 2
\ No newline at end of file
......@@ -25,19 +25,12 @@ set_property PACKAGE_PIN T2 [get_ports SFP0_RX_P]
set_property PACKAGE_PIN T1 [get_ports SFP0_RX_N]
set_property PACKAGE_PIN U4 [get_ports SFP0_TX_P]
set_property PACKAGE_PIN V2 [get_ports SFP1_RX_P]
set_property PACKAGE_PIN V1 [get_ports SFP1_RX_N]
set_property PACKAGE_PIN W4 [get_ports SFP1_TX_P]
set_property PACKAGE_PIN W3 [get_ports SFP1_TX_N]
## SFP CONTROL:
##-------------
# IO_0_12
set_property PACKAGE_PIN AL8 [get_ports SFP0_TX_DISABLE]
set_property IOSTANDARD LVCMOS18 [get_ports SFP0_TX_DISABLE]
set_property PACKAGE_PIN AM9 [get_ports SFP1_TX_DISABLE]
set_property IOSTANDARD LVCMOS18 [get_ports SFP1_TX_DISABLE]
##====================##
## SIGNALS FORWARDING ##
......@@ -53,15 +46,4 @@ set_property SLEW FAST [get_ports USER_SMA_GPIO_P]
set_property PACKAGE_PIN G27 [get_ports USER_SMA_GPIO_N]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SMA_GPIO_N]
set_property SLEW FAST [get_ports USER_SMA_GPIO_N]
##===================================================================================================##
##===================================================================================================##
#set_false_path -to [get_pins -hier -filter {NAME =~ *debug*/D}]
#set_false_path -to [get_pins -hier -filter {NAME =~ *debug*/D}]
#set_false_path -from [get_pins -hier -filter {NAME =~ vio*}]
#set_false_path -to [get_pins -hier -filter {NAME =~ vio*}]
#set_multicycle_path -end -from [get_pins -hier -filter {NAME =~lpgbtFpga_top_inst/rxGearbox_5g12_inst/dat_outFrame_o_reg[*]/C}] -to [get_pins -hier -filter {NAME =~uplinkstimulis_top_inst/*/D}] 8
\ No newline at end of file
set_property SLEW FAST [get_ports USER_SMA_GPIO_N]
\ No newline at end of file
/* *****************************************************************************
* lpGBTX *
* Copyright (C) 2011-2016 GBTX Team, CERN *
* *
* This IP block is free for HEP experiments and other scientific research *
* purposes. Commercial exploitation of a chip containing the IP is not *
* permitted. You can not redistribute the IP without written permission *
* from the authors. Any modifications of the IP have to be communicated back *
* to the authors. The use of the IP should be acknowledged in publications, *
* public presentations, user manual, and other documents. *
* *
* This IP is distributed in the hope that it will be useful, but WITHOUT ANY *
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
*******************************************************************************
*
* file: downLinkDeinterleaver.v
*
* downLinkDeinterleaver
*
* History:
* 2016/05/20 Szymon Kulis : Created
* 2016/12/20 Szymon Kulis : Data muxing (bert) removed
*
**/
module LpGBT_Model_dataPath (
// Clocks inputs:
input downClki,
input upClki,
input upLinkDataPathEnable,
input downLinkDataPathEnable,
// -------------------------------------------------------------------------
// - Down link -------------------------------------------------------------
// -------------------------------------------------------------------------
// data input
input [63:0] downLinkFrame,
// data outputs
output [15:0] downLinkDataGroup0,
output [15:0] downLinkDataGroup1,
output [1:0] downLinkDataEc,
output [1:0] downLinkDataIc,
output [3:0] downLinkHeader,
// control signals
input downLinkBypassDeinterleaver,
input downLinkBypassFECDecoder,
input downLinkBypassDescsrambler,
// -- fec counter --
input enableFECErrCounter,
output [15:0] fecCorrectionCount,
// -------------------------------------------------------------------------
// - Up link ---------------------------------------------------------------
// -------------------------------------------------------------------------
// input data:
input [31:0] upLinkData0,
input [31:0] upLinkData1,
input [31:0] upLinkData2,
input [31:0] upLinkData3,
input [31:0] upLinkData4,
input [31:0] upLinkData5,
input [31:0] upLinkData6,
input [1:0] upLinkDataIC,
input [1:0] upLinkDataEC,
// controll signals
input upLinkScramblerBypass,
input upLinkScramblerReset,
input upLinkFecBypass,
input upLinkInterleaverBypass,
input fecMode,
input txDataRate,
// output data
output [255:0] upLinkFrame
);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg default triplicate
// tmrg do_not_triplicate upLinkFrame
// tmrg do_not_triplicate downLinkFrame
// -------------------------------------------------------------------------- //
wire upLinkClk = upClki & upLinkDataPathEnable;
wire downLinkClk = downClki & downLinkDataPathEnable;
wire [31:0] downLinkData;
assign downLinkDataGroup1=downLinkData[31:16];
assign downLinkDataGroup0=downLinkData[15:0];
downLinkDataPath DLDP (
.bypassDeinterleaver(downLinkBypassDeinterleaver),
.bypassDescrambler(downLinkBypassDescsrambler),
.bypassFECDecoder(downLinkBypassFECDecoder),
.clk(downLinkClk),
.dataEC(downLinkDataEc),
.dataIC(downLinkDataIc),
.dataOut(downLinkData),
.downLinkFrame(downLinkFrame),
.enableFECErrCounter(enableFECErrCounter),
.fecCorrectionCount(fecCorrectionCount),
.header(downLinkHeader)
);
wire [5:0] txDummyFec5 = 6'b001100;// TODO FIXME check the values !!
wire [9:0] txDummyFec12= 10'b0101010101;// TODO FIXME check the values !!
wire [111:0] upLinkDataLow, upLinkDataHigh;
assign upLinkDataLow[0+:16] = upLinkData0[0 +: 16];
assign upLinkDataLow[16+:16] = upLinkData1[0 +: 16];
assign upLinkDataLow[32+:16] = upLinkData2[0 +: 16];
assign upLinkDataLow[48+:16] = upLinkData3[0 +: 16];
assign upLinkDataLow[64+:16] = upLinkData4[0 +: 16];
assign upLinkDataLow[80+:16] = upLinkData5[0 +: 16];
assign upLinkDataLow[96+:16] = upLinkData6[0 +: 16];
assign upLinkDataHigh[0+:16] = upLinkData0[16+: 16];
assign upLinkDataHigh[16+:16] = upLinkData1[16+: 16];
assign upLinkDataHigh[32+:16] = upLinkData2[16+: 16];
assign upLinkDataHigh[48+:16] = upLinkData3[16+: 16];
assign upLinkDataHigh[64+:16] = upLinkData4[16+: 16];
assign upLinkDataHigh[80+:16] = upLinkData5[16+: 16];
assign upLinkDataHigh[96+:16] = upLinkData6[16+: 16];
upLinkDataPath ULDP (
.clk40M(upLinkClk),
.txData0(upLinkData0),
.txData1(upLinkData1),
.txData2(upLinkData2),
.txData3(upLinkData3),
.txData4(upLinkData4),
.txData5(upLinkData5),
.txData6(upLinkData6),
.txIC(upLinkDataIC),
.txEC(upLinkDataEC),
.txDummyFec5(6'd0),
.txDummyFec12(10'd0),
.scramblerBypass(upLinkScramblerBypass),
.interleaverBypass(upLinkInterleaverBypass),
.fecBypass(upLinkFecBypass),
.fecMode(fecMode),
.txDataRate(txDataRate),
.scramblerReset(upLinkScramblerReset),
.upLinkFrame(upLinkFrame)
);
endmodule
/** ****************************************************************************
* lpGBTX *
* Copyright (C) 2011-2016 GBTX Team, CERN *
* *
* This IP block is free for HEP experiments and other scientific research *
* purposes. Commercial exploitation of a chip containing the IP is not *
* permitted. You can not redistribute the IP without written permission *
* from the authors. Any modifications of the IP have to be communicated back *
* to the authors. The use of the IP should be acknowledged in publications, *
* public presentations, user manual, and other documents. *
* *
* This IP is distributed in the hope that it will be useful, but WITHOUT ANY *
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
*******************************************************************************
*
* file: upCounter.v
*
* upCounter
*
* History:
* 2016/05/21 Szymon Kulis : Created
*
**/
module dataPathFecCounter(
input enable,
input clk,
input [15:0] addValue,
output reg [15:0] count
);
// tmrg do_not_touch
reg clkGate;
wire rst=!enable;
wire clkGated=clk&clkGate;
wire enableVoted=enable;
reg [16:0] countNext;
wire [16:0] countNextVoted=countNext;
// latch for clock gate
always @(clk or enable)
if(!clk)
clkGate=enable;
// counter register
always @(posedge clk or posedge rst)
if (rst)
count <= 16'b0;
else
count <= countNextVoted;
// next state logic
always @(count or enable or addValue)
begin
if (!enable)
countNext=0;
else
countNext=count+addValue;
if (countNext>17'hffff)
countNext=17'hffff;
end
endmodule
/* Module: Descrambler36bitOrder36 */
/* Created: Paulo Moreira, 2015/09/15 */
/* Institute: CERN */
/* Version: 1.0 */
/* Descrambler width: 36 - bits */
/* Descrambler order: 36 */
/* Recursive equation used for the scrambler: Si = Di xnor Si-25 xnor Si-36 */
`timescale 1 ps / 1 ps
module descrambler36bitOrder36(
input [35:0] scrambledData,
input clock,
input bypass,
output reg [35:0] descrambledData
);
reg [35:0] memoryRegister;
wire [35:0] iMemoryRegister;
wire [35:0] iMemoryRegisterVoted = iMemoryRegister;
wire [35:0] iDescrambledData;
wire [35:0] iDescrambledDataVoted = iDescrambledData;
always @(posedge clock)
begin
memoryRegister <= iMemoryRegisterVoted;
descrambledData <= iDescrambledDataVoted;
end
// Descrambler polynomial and bypass mux
assign
iDescrambledData[35:25] = (bypass)? scrambledData[35:25] : scrambledData[35:25] ~^ scrambledData[10:0] ~^ memoryRegister[35:25],
iDescrambledData[24:0] = (bypass)? scrambledData[34:0] : scrambledData[24:0] ~^ memoryRegister[35:11] ~^ memoryRegister[24:0],
iMemoryRegister[35:0] = (bypass)? 36'h000000000 : scrambledData[35:0];
endmodule
/** ****************************************************************************
* lpGBTX *
* Copyright (C) 2011-2016 GBTX Team, CERN *
* *
* This IP block is free for HEP experiments and other scientific research *
* purposes. Commercial exploitation of a chip containing the IP is not *
* permitted. You can not redistribute the IP without written permission *
* from the authors. Any modifications of the IP have to be communicated back *
* to the authors. The use of the IP should be acknowledged in publications, *
* public presentations, user manual, and other documents. *
* *
* This IP is distributed in the hope that it will be useful, but WITHOUT ANY *
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
*******************************************************************************
*
* file: downLinkDeinterleaver.v
*
* downLinkDeinterleaver
*
* History:
* 2016/05/20 Szymon Kulis : Created
* 2016/11/02 José Fonseca : Modified
*
**/
module downLinkDataPath (
// Clocks inputs:
input clk,
// data input
input [63:0] downLinkFrame,
// data outputs
output [31:0] dataOut,
output [1:0] dataEC,
output [1:0] dataIC,
output [3:0] header,
// control signals
input bypassDeinterleaver,
input bypassFECDecoder,
input bypassDescrambler,
// -- fec counter --
input enableFECErrCounter,
output [15:0] fecCorrectionCount
);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg default triplicate
// tmrg do_not_triplicate downLinkFrame
// -------------------------------------------------------------------------- //
wire [35:0] dataDeint;
wire [23:0] fecDeint;
wire [35:0] decData;
reg [35:0] decDataReg;
wire [35:0] descrambledData;
reg [63:0] downLinkFrameReg;
downLinkDeinterleaver DLD (
.bypass(bypassDeinterleaver),
.downLinkFrame(downLinkFrame),
.data(dataDeint),
.fec(fecDeint)
);
downLinkFECDecoder DLFD (
.clk(clk),
.bypass(bypassFECDecoder),
.enableFECErrCounter(enableFECErrCounter),
.data(dataDeint),
.fec(fecDeint),
.dataOut(decData),
.fecCorrectionCount(fecCorrectionCount)
);
descrambler36bitOrder36 DES (
.bypass(bypassDescrambler),
.clock(clk),
.scrambledData(decData),
.descrambledData(descrambledData)
);
/*
downLinkBERT DLBERT(
.enable(enableBERT),
.clk(clk40M),
.dataIn(descrambledData[31:0]),
.pattern(bertPattern),
.errCount(bertCount)
);
*/
assign dataOut = descrambledData[31:0];
assign dataEC = descrambledData[33:32];
assign dataIC = descrambledData[35:34];
// assign header = downLinkFrame[63:60]; // version with the header in front
assign header = {downLinkFrame[63],downLinkFrame[61],downLinkFrame[59],downLinkFrame[57]}; // header interleaved with data for DC balance
endmodule
/** ****************************************************************************
* lpGBTX *
* Copyright (C) 2011-2016 GBTX Team, CERN *
* *
* This IP block is free for HEP experiments and other scientific research *
* purposes. Commercial exploitation of a chip containing the IP is not *
* permitted. You can not redistribute the IP without written permission *
* from the authors. Any modifications of the IP have to be communicated back *
* to the authors. The use of the IP should be acknowledged in publications, *
* public presentations, user manual, and other documents. *
* *
* This IP is distributed in the hope that it will be useful, but WITHOUT ANY *
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
*******************************************************************************
*
* file: downLinkDeinterleaver.v
*
* downLinkDeinterleaver
*
* History:
* 2016/05/20 Szymon Kulis : Created
* 2016/11/02 José Fonseca : Modified
*
**/
module downLinkDeinterleaver (
input bypass,
input [63:0] downLinkFrame,
output [35:0] data,
output [23:0] fec
);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// -------------------------------------------------------------------------- //
// Code 0
assign data[8:0] = (bypass) ? downLinkFrame[32:24] : {downLinkFrame[50:48], downLinkFrame[38:36], downLinkFrame[26:24]};
assign fec[5:0] = (bypass) ? downLinkFrame[5:0] : {downLinkFrame[14:12], downLinkFrame[2:0]};
// Code 1
assign data[17:9] = (bypass) ? downLinkFrame[41:33] : {downLinkFrame[53:51], downLinkFrame[41:39], downLinkFrame[29:27]};
assign fec[11:6] = (bypass) ? downLinkFrame[11:6] : {downLinkFrame[17:15], downLinkFrame[5:3]};
// Code 2
assign data[26:18] = (bypass) ? downLinkFrame[50:42] : {downLinkFrame[56:54], downLinkFrame[44:42], downLinkFrame[32:30]};
assign fec[17:12] = (bypass) ? downLinkFrame[17:12] : {downLinkFrame[20:18], downLinkFrame[8:6]};
// Code 3
assign data[35:27] = (bypass) ? {downLinkFrame[62], downLinkFrame[60], downLinkFrame[58], downLinkFrame[56:51]} : {downLinkFrame[62], downLinkFrame[60], downLinkFrame[58], downLinkFrame[47:45], downLinkFrame[35:33]};
assign fec[23:18] = (bypass) ? downLinkFrame[23:18] : {downLinkFrame[23:21], downLinkFrame[11:9]};
endmodule
/** ****************************************************************************
* lpGBTX *
* Copyright (C) 2011-2016 GBTX Team, CERN *
* *
* This IP block is free for HEP experiments and other scientific research *
* purposes. Commercial exploitation of a chip containing the IP is not *
* permitted. You can not redistribute the IP without written permission *
* from the authors. Any modifications of the IP have to be communicated back *
* to the authors. The use of the IP should be acknowledged in publications, *
* public presentations, user manual, and other documents. *
* *
* This IP is distributed in the hope that it will be useful, but WITHOUT ANY *
* WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
*******************************************************************************
*
* file: downLinkFECDecoder.v
*
* downLinkFECDecoder
*
* History:
* 2016/05/20 Szymon Kulis : Created
* 2016/11/02 José Fonseca : Modified
*
**/
module downLinkFECDecoder (
input clk,
input bypass,
input enableFECErrCounter,
input [35:0] data,
input [23:0] fec,
output [35:0] dataOut,
output [15:0] fecCorrectionCount
);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
wire [20:0] virtualFrame_C0;
wire [20:0] virtualFrame_C1;
wire [20:0] virtualFrame_C2;
wire [20:0] virtualFrame_C3;
wire [14:0] decData_C0;
wire [14:0] decData_C1;
wire [14:0] decData_C2;
wire [14:0] decData_C3;
wire [1:0] fecErrorSub0;
wire [1:0] fecErrorSub1;
wire [1:0] fecErrorSub2;
wire [1:0] fecErrorSub3;
assign virtualFrame_C0 = {fec[5:0], 6'b0, data[8:0]};
assign virtualFrame_C1 = {fec[11:6], 6'b0, data[17:9]};
assign virtualFrame_C2 = {fec[17:12], 6'b0, data[26:18]};
assign virtualFrame_C3 = {fec[23:18], 6'b0, data[35:27]};
rs_decoder_N7K5 RSD0 (
.msgInput(virtualFrame_C0),
.error(fecErrorSub0),
.decMsg(decData_C0)
);
rs_decoder_N7K5 RSD1 (
.msgInput(virtualFrame_C1),
.error(fecErrorSub1),
.decMsg(decData_C1)
);
rs_decoder_N7K5 RSD2 (
.msgInput(virtualFrame_C2),
.error(fecErrorSub2),
.decMsg(decData_C2)
);
rs_decoder_N7K5 RSD3 (
.msgInput(virtualFrame_C3),
.error(fecErrorSub3),
.decMsg(decData_C3)
);
wire [15:0] fecCounterAddValue = fecErrorSub0+fecErrorSub1+fecErrorSub2+fecErrorSub3;
dataPathFecCounter EC(
.enable(enableFECErrCounter),
.clk(clk),
.addValue(fecCounterAddValue),
.count(fecCorrectionCount)
);
assign dataOut = (bypass) ? data : {decData_C3[8:0], decData_C2[8:0], decData_C1[8:0], decData_C0[8:0]};
endmodule
module gf_add_3(op1, op2, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [2:0] op1;
input [2:0] op2;
output [2:0] res;
assign res = op1 ^ op2;
endmodule
module gf_add_4(op1, op2, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [3:0] op1;
input [3:0] op2;
output [3:0] res;
assign res = op1 ^ op2;
endmodule
module gf_add_5(op1, op2, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [4:0] op1;
input [4:0] op2;
output [4:0] res;
assign res = op1 ^ op2;
endmodule
module gf_inv_3(op, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [2:0] op;
output reg [2:0] res;
always @(op) begin
case(op)
3'd0 :
res = 3'd0;
3'd1 :
res = 3'd1;
3'd2 :
res = 3'd5;
3'd3 :
res = 3'd6;
3'd4 :
res = 3'd7;
3'd5 :
res = 3'd2;
3'd6 :
res = 3'd3;
3'd7 :
res = 3'd4;
endcase
end
endmodule
module gf_inv_5(op, res);
input [4:0] op;
output reg [4:0] res;
always @(*) begin
case(op)
5'd0 :
res = 5'd0;
5'd1 :
res = 5'd1;
5'd2 :
res = 5'd18;
5'd3 :
res = 5'd28;
5'd4 :
res = 5'd9;
5'd5 :
res = 5'd23;
5'd6 :
res = 5'd14;
5'd7 :
res = 5'd12;
5'd8 :
res = 5'd22;
5'd9 :
res = 5'd4;
5'd10 :
res = 5'd25;
5'd11 :
res = 5'd16;
5'd12 :
res = 5'd7;
5'd13 :
res = 5'd15;
5'd14 :
res = 5'd6;
5'd15 :
res = 5'd13;
5'd16 :
res = 5'd11;
5'd17 :
res = 5'd24;
5'd18 :
res = 5'd2;
5'd19 :
res = 5'd29;
5'd20 :
res = 5'd30;
5'd21 :
res = 5'd26;
5'd22 :
res = 5'd8;
5'd23 :
res = 5'd5;
5'd24 :
res = 5'd17;
5'd25 :
res = 5'd10;
5'd26 :
res = 5'd21;
5'd27 :
res = 5'd31;
5'd28 :
res = 5'd3;
5'd29 :
res = 5'd19;
5'd30 :
res = 5'd20;
5'd31 :
res = 5'd27;
endcase
end
endmodule
module gf_log_3(op, err, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [2:0] op;
output reg err;
output reg [2:0] res;
always @(op) begin
case(op)
3'd0 :
begin
err = 1;
res = 3'd0;
end
3'd1 :
begin
err = 0;
res = 3'd0;
end
3'd2 :
begin
err = 0;
res = 3'd1;
end
3'd3 :
begin
err = 0;
res = 3'd3;
end
3'd4 :
begin
err = 0;
res = 3'd2;
end
3'd5 :
begin
err = 0;
res = 3'd6;
end
3'd6 :
begin
err = 0;
res = 3'd4;
end
3'd7 :
begin
err = 0;
res = 3'd5;
end
endcase
end
endmodule
module gf_log_5(op, err, res);
input [4:0] op;
output reg err;
output reg [4:0] res;
always @(*) begin
case(op)
5'd0 :
begin
err = 1;
res = 5'd0;
end
5'd1 :
begin
err = 0;
res = 5'd0;
end
5'd2 :
begin
err = 0;
res = 5'd1;
end
5'd3 :
begin
err = 0;
res = 5'd18;
end
5'd4 :
begin
err = 0;
res = 5'd2;
end
5'd5 :
begin
err = 0;
res = 5'd5;
end
5'd6 :
begin
err = 0;
res = 5'd19;
end
5'd7 :
begin
err = 0;
res = 5'd11;
end
5'd8 :
begin
err = 0;
res = 5'd3;
end
5'd9 :
begin
err = 0;
res = 5'd29;
end
5'd10 :
begin
err = 0;
res = 5'd6;
end
5'd11 :
begin
err = 0;
res = 5'd27;
end
5'd12 :
begin
err = 0;
res = 5'd20;
end
5'd13 :
begin
err = 0;
res = 5'd8;
end
5'd14 :
begin
err = 0;
res = 5'd12;
end
5'd15 :
begin
err = 0;
res = 5'd23;
end
5'd16 :
begin
err = 0;
res = 5'd4;
end
5'd17 :
begin
err = 0;
res = 5'd10;
end
5'd18 :
begin
err = 0;
res = 5'd30;
end
5'd19 :
begin
err = 0;
res = 5'd17;
end
5'd20 :
begin
err = 0;
res = 5'd7;
end
5'd21 :
begin
err = 0;
res = 5'd22;
end
5'd22 :
begin
err = 0;
res = 5'd28;
end
5'd23 :
begin
err = 0;
res = 5'd26;
end
5'd24 :
begin
err = 0;
res = 5'd21;
end
5'd25 :
begin
err = 0;
res = 5'd25;
end
5'd26 :
begin
err = 0;
res = 5'd9;
end
5'd27 :
begin
err = 0;
res = 5'd16;
end
5'd28 :
begin
err = 0;
res = 5'd13;
end
5'd29 :
begin
err = 0;
res = 5'd14;
end
5'd30 :
begin
err = 0;
res = 5'd24;
end
5'd31 :
begin
err = 0;
res = 5'd15;
end
endcase
end
endmodule
module gf_multBy2_3(op, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [2:0] op;
output reg [2:0] res;
always @(op) begin
res = {op[1], op[0]^op[2], op[2]};
end
endmodule
module gf_multBy2_4(op, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [3:0] op;
output [3:0] res;
assign res[0] = op[3];
assign res[1] = op[0] ^ op[3];
assign res[2] = op[1];
assign res[3] = op[2];
endmodule
module gf_multBy2_5(op, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [4:0] op;
output [4:0] res;
assign res[0] = op[4];
assign res[1] = op[0];
assign res[2] = op[1] ^ op[4];
assign res[3] = op[2];
assign res[4] = op[3];
endmodule
module gf_multBy3_4(op, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [3:0] op;
output [3:0] res;
assign res[0] = op[3] ^ op[0];
assign res[1] = op[1] ^ op[0] ^ op[3];
assign res[2] = op[2] ^ op[1];
assign res[3] = op[3] ^ op[2];
endmodule
module gf_multBy3_5(op, res);
// -------------------------------------------------------------------------- //
// ------------- Triple Modular Redundancy Generator Directives ------------- //
// -------------------------------------------------------------------------- //
// tmrg do_not_touch
// -------------------------------------------------------------------------- //
input [4:0] op;
output [4:0] res;
assign res[0] = op[4] ^ op[0];
assign res[1] = op[1] ^ op[0];
assign res[2] = op[2] ^ op[1] ^ op[4];
assign res[3] = op[3] ^ op[2];
assign res[4] = op[4] ^ op[3];
endmodule
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