Skip to content
Snippets Groups Projects
Commit e0b8588c authored by Julian Maxime Mendez's avatar Julian Maxime Mendez
Browse files

- Update lpgbt-fpga commit

- Update project name
- Update readme
parent 2f48447e
No related branches found
No related tags found
1 merge request!1Resolve "Cleaning: move the LpGBT emulator to a dedicated project"
Subproject commit c1e433e987bd1c6986dde7b8a28c266769acbe26 Subproject commit 0e64989403c6114303c7aee14cafeb91264c1809
...@@ -29,7 +29,28 @@ to help the user in designing its own system in the most efficient way. **Exampl ...@@ -29,7 +29,28 @@ to help the user in designing its own system in the most efficient way. **Exampl
* **LpGBT-FPGA**: This folder contains the VHDL files that describe the logic of the different modules required to implements the IP (Encoder/Decoder, Scrambler/Descrambler, Gearboxes, Frame aligner) * **LpGBT-FPGA**: This folder contains the VHDL files that describe the logic of the different modules required to implements the IP (Encoder/Decoder, Scrambler/Descrambler, Gearboxes, Frame aligner)
* **Mgt**: This folder contains the Mgt module used to serialize/deserialize the data. In the case of the KCU105 design, it contains a GTH Transceiver (Xilinx). * **Mgt**: This folder contains the Mgt module used to serialize/deserialize the data. In the case of the KCU105 design, it contains a GTH Transceiver (Xilinx).
* **TCL**: This folder contains the TCL script that defines the procedure to compile and simulate the project * **TCL**: This folder contains the TCL script that defines the procedure to compile and simulate the project
* **TestBench_sim**: This folder contains all of the file required to implement the LpGBT-FPGA modules within a complete testbench (LpGBT-FPGA top level, Stimulis, Codecs from the LpGBT Asic model, ...). * **Constraints**: IO and timming constraints
* **hdl**: VHDL sources of example design's files (LpGBT-FPGA top level, Stimulis, ...).
## How-to
The vivado folder includes two projects:
- lpgbt-fpga-kcu105-10g24: configured to work with an uplink running at 10g24.
- lpgbt-fpga-kcu105-5g12: configured to work with an uplink running at 5g12.
> **Tip:** By default, the design are configured to work in FEC5 mode. To compile it for FEC12, you have to change the value of the FEC generic in the `lpgbt_fpga_kcu105_10g24` or `lpgbt_fpga_kcu105_5g12` file to `FEC12`.
> **Tip:** Before using the example designs, the users have to update the GBT-SC submodule using the following terminal commands:
> ```
> cd LpGBT-FPGA
> git submodule init
> git submodule update
> ```
> Or using tortoise git:
> ```
> right click > TortoiseGit > Submodule Update
> ```
## KCU105 testbench ## KCU105 testbench
......
-------------------------------------------------------
--! @file
--! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
--! @version 1.0
--! @brief LpGBT-FPGA Top
-------------------------------------------------------
--! Include the IEEE VHDL standard library
library ieee;
use ieee.std_logic_1164.all;
--! Include the LpGBT-FPGA specific package
use work.lpgbtfpga_package.all;
--! Xilinx devices library:
library unisim;
use unisim.vcomponents.all;
entity lpgbtFpga_top is
GENERIC (
DATARATE : integer range 0 to 2 := DATARATE_5G12; --! Datarate selection can be: DATARATE_10G24 or DATARATE_5G12
FEC : integer range 0 to 2 := FEC5 --! FEC selection can be: FEC5 or FEC12
);
PORT (
-- Clocks
donwlinkClk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
uplinkClk_o : out std_logic; --! Clock provided by the Rx serdes: in phase with data
uplinkClkEn_o : out std_logic; --! Clock enable pulsed when new data is ready
downlinkRst_i : in std_logic; --! Reset the downlink path
uplinkRst_i : in std_logic; --! Reset the uplink path
-- Down link
downlinkUserData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
downlinkEcData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
downlinkIcData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
downLinkBypassInterleaver_i : in std_logic; --! Bypass downlink interleaver (test purpose only)
downLinkBypassFECEncoder_i : in std_logic; --! Bypass downlink FEC (test purpose only)
downLinkBypassScrambler_i : in std_logic; --! Bypass downlink scrambler (test purpose only)
downlinkReady_o : out std_logic; --! Downlink ready status
-- Up link
uplinkUserData_o : out std_logic_vector(229 downto 0); --! Uplink data (user)
uplinkEcData_o : out std_logic_vector(1 downto 0); --! Uplink EC field
uplinkIcData_o : out std_logic_vector(1 downto 0); --! Uplink IC field
uplinkSelectDataRate_i : in std_logic; --! Uplink datarate selection (dynamic mode only - '0': 5.12Gbps / '1': 10.24Gbps)
uplinkSelectFEC_i : in std_logic; --! Uplink FEC selection (dynamic mode only - '0': FEC5 / '1': FEC12)
uplinkBypassInterleaver_i : in std_logic; --! Bypass uplink interleaver (test purpose only)
uplinkBypassFECEncoder_i : in std_logic; --! Bypass uplink FEC (test purpose only)
uplinkBypassScrambler_i : in std_logic; --! Bypass uplink scrambler (test purpose only)
uplinkReady_o : out std_logic; --! Uplink ready status
-- MGT
clk_mgtrefclk_i : in std_logic; --! Transceiver serial clock
clk_mgtfreedrpclk_i : in std_logic;
clk_mgtTxClk_o : out std_logic;
clk_mgtRxClk_o : out std_logic;
mgt_rxn_i : in std_logic;
mgt_rxp_i : in std_logic;
mgt_txn_o : out std_logic;
mgt_txp_o : out std_logic;
mgt_txcaliben_i : in std_logic;
mgt_txcalib_i : in std_logic_vector(6 downto 0);
mgt_txaligned_o : out std_logic;
mgt_txphase_o : out std_logic_vector(6 downto 0)
);
end lpgbtFpga_top;
--=================================================================================================--
--#################################### Architecture ###########################################--
--=================================================================================================--
architecture behavioral of lpgbtFpga_top is
COMPONENT mgt
port (
--=============--
-- Clocks --
--=============--
MGT_REFCLK_i : in std_logic;
MGT_FREEDRPCLK_i : in std_logic;
MGT_RXUSRCLK_o : out std_logic;
MGT_TXUSRCLK_o : out std_logic;
--=============--
-- Resets --
--=============--
MGT_TXRESET_i : in std_logic;
MGT_RXRESET_i : in std_logic;
--=============--
-- Control --
--=============--
MGT_RXSlide_i : in std_logic;
MGT_ENTXCALIBIN_i : in std_logic;
MGT_TXCALIB_i : in std_logic_vector(6 downto 0);
--=============--
-- Status --
--=============--
MGT_TXREADY_o : out std_logic;
MGT_RXREADY_o : out std_logic;
MGT_TX_ALIGNED_o : out std_logic;
MGT_TX_PIPHASE_o : out std_logic_vector(6 downto 0);
--==============--
-- Data --
--==============--
MGT_USRWORD_i : in std_logic_vector(31 downto 0);
MGT_USRWORD_o : out std_logic_vector(31 downto 0);
--===============--
-- Serial intf. --
--===============--
RXn_i : in std_logic;
RXp_i : in std_logic;
TXn_o : out std_logic;
TXp_o : out std_logic
);
END COMPONENT;
COMPONENT LpGBTFPGA_Downlink
GENERIC(
-- Expert parameters
c_multicyleDelay : integer range 0 to 7 := 3; --! Multicycle delay
c_clockRatio : integer := 8; --! Clock ratio is clock_out / 40 (shall be an integer - E.g.: 320/40 = 8)
c_outputWidth : integer --! Transceiver's word size
);
port (
-- Clocks
clk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
clkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
rst_n_i : in std_logic; --! Downlink reset signal (Tx ready from the transceiver)
-- Down link
userData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
ECData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
ICData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
-- Output
mgt_word_o : out std_logic_vector((c_outputWidth-1) downto 0); --! Downlink encoded frame (IC + EC + User Data + FEC)
-- Configuration
interleaverBypass_i : in std_logic; --! Bypass downlink interleaver (test purpose only)
encoderBypass_i : in std_logic; --! Bypass downlink FEC (test purpose only)
scramblerBypass_i : in std_logic; --! Bypass downlink scrambler (test purpose only)
-- Status
rdy_o : out std_logic --! Downlink ready status
);
END COMPONENT;
COMPONENT LpGBTFPGA_Uplink
GENERIC(
-- General configuration
DATARATE : integer range 0 to 2 := DATARATE_5G12; --! Datarate selection can be: DATARATE_10G24 or DATARATE_5G12
FEC : integer range 0 to 2 := FEC5; --! FEC selection can be: FEC5 or FEC12
-- Expert parameters
c_multicyleDelay : integer range 0 to 7 := 3; --! Multicycle delay
c_clockRatio : integer; --! Clock ratio is mgt_userclk / 40 (shall be an integer)
c_mgtWordWidth : integer; --! Bus size of the input word
c_allowedFalseHeader : integer; --! Number of false header allowed to avoid unlock on frame error
c_allowedFalseHeaderOverN : integer; --! Number of header checked to know wether the lock is lost or not
c_requiredTrueHeader : integer; --! Number of true header required to go in locked state
c_bitslip_mindly : integer := 1; --! Number of clock cycle required when asserting the bitslip signal
c_bitslip_waitdly : integer := 40 --! Number of clock cycle required before being back in a stable state
);
PORT (
-- Clock and reset
clk_freeRunningClk_i : in std_logic;
uplinkClk_i : in std_logic; --! Input clock (Rx user clock from transceiver)
uplinkClkOutEn_o : out std_logic; --! Clock enable to be used in the user's logic
uplinkRst_n_i : in std_logic; --! Uplink reset signal (Rx ready from the transceiver)
-- Input
mgt_word_o : in std_logic_vector((c_mgtWordWidth-1) downto 0); --! Input frame coming from the MGT
-- Data
userData_o : out std_logic_vector(229 downto 0); --! User output (decoded data). The payload size varies depending on the
--! datarate/FEC configuration:
--! * *FEC5 / 5.12 Gbps*: 112bit
--! * *FEC12 / 5.12 Gbps*: 98bit
--! * *FEC5 / 10.24 Gbps*: 230bit
--! * *FEC12 / 10.24 Gbps*: 202bit
EcData_o : out std_logic_vector(1 downto 0); --! EC field value received from the LpGBT
IcData_o : out std_logic_vector(1 downto 0); --! IC field value received from the LpGBT
-- Control
bypassInterleaver_i : in std_logic; --! Bypass uplink interleaver (test purpose only)
bypassFECEncoder_i : in std_logic; --! Bypass uplink FEC (test purpose only)
bypassScrambler_i : in std_logic; --! Bypass uplink scrambler (test purpose only)
-- Transceiver control
mgt_bitslipCtrl_o : out std_logic; --! Control the Bitslib/RxSlide port of the Mgt
-- Status
dataCorrected_o : out std_logic_vector(229 downto 0); --! Flag allowing to know which bit(s) were toggled by the FEC
IcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the IC field were toggled by the FEC
EcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the EC field were toggled by the FEC
rdy_o : out std_logic --! Ready signal from the uplink decoder
);
END COMPONENT;
signal downlink_mgtword_s : std_logic_vector(31 downto 0);
signal uplink_mgtword_s : std_logic_vector(31 downto 0);
signal mgt_rxslide_s : std_logic;
signal mgt_txrdy_s : std_logic;
signal mgt_rxrdy_s : std_logic;
signal clk_mgtRxClk_s : std_logic;
begin --========#### Architecture Body ####========--
LpGBTFPGA_Downlink_inst: LpGBTFPGA_Downlink
GENERIC MAP(
-- Expert parameters
c_multicyleDelay => 3,
c_clockRatio => 8,
c_outputWidth => 32
)
PORT MAP(
-- Clocks
clk_i => donwlinkClk_i,
clkEn_i => downlinkClkEn_i,
rst_n_i => mgt_txrdy_s,
-- Down link
userData_i => downlinkUserData_i,
ECData_i => downlinkEcData_i,
ICData_i => downlinkIcData_i,
-- Output
mgt_word_o => downlink_mgtword_s,
-- Configuration
interleaverBypass_i => downLinkBypassInterleaver_i,
encoderBypass_i => downLinkBypassFECEncoder_i,
scramblerBypass_i => downLinkBypassScrambler_i,
-- Status
rdy_o => downlinkReady_o
);
mgt_inst: mgt
port map(
--=============--
-- Clocks --
--=============--
MGT_REFCLK_i => clk_mgtrefclk_i,
MGT_FREEDRPCLK_i => clk_mgtfreedrpclk_i,
MGT_RXUSRCLK_o => clk_mgtRxClk_s,
MGT_TXUSRCLK_o => clk_mgtTxClk_o,
--=============--
-- Resets --
--=============--
MGT_TXRESET_i => downlinkRst_i,
MGT_RXRESET_i => uplinkRst_i,
--=============--
-- Control --
--=============--
MGT_RXSlide_i => mgt_rxslide_s,
MGT_ENTXCALIBIN_i => '0',
MGT_TXCALIB_i => (others => '0'),
--=============--
-- Status --
--=============--
MGT_TXREADY_o => mgt_txrdy_s,
MGT_RXREADY_o => mgt_rxrdy_s,
MGT_TX_ALIGNED_o => open,
MGT_TX_PIPHASE_o => open,
--==============--
-- Data --
--==============--
MGT_USRWORD_i => downlink_mgtword_s,
MGT_USRWORD_o => uplink_mgtword_s,
--===============--
-- Serial intf. --
--===============--
RXn_i => mgt_rxn_i,
RXp_i => mgt_rxp_i,
TXn_o => mgt_txn_o,
TXp_o => mgt_txp_o
);
uplinkClk_o <= clk_mgtRxClk_s;
clk_mgtRxClk_o <= clk_mgtRxClk_s;
LpGBTFPGA_Uplink_inst: LpGBTFPGA_Uplink
GENERIC MAP(
-- General configuration
DATARATE => DATARATE,
FEC => FEC,
-- Expert parameters
c_multicyleDelay => 3,
c_clockRatio => 8,
c_mgtWordWidth => 32,
c_allowedFalseHeader => 5,
c_allowedFalseHeaderOverN => 64,
c_requiredTrueHeader => 30,
c_bitslip_mindly => 1,
c_bitslip_waitdly => 40
)
PORT MAP(
-- Clock and reset
clk_freeRunningClk_i => clk_mgtfreedrpclk_i,
uplinkClk_i => clk_mgtRxClk_s,
uplinkClkOutEn_o => uplinkClkEn_o,
uplinkRst_n_i => mgt_rxrdy_s,
-- Input
mgt_word_o => uplink_mgtword_s,
-- Data
userData_o => uplinkUserData_o,
EcData_o => uplinkEcData_o,
IcData_o => uplinkIcData_o,
-- Control
bypassInterleaver_i => uplinkBypassInterleaver_i,
bypassFECEncoder_i => uplinkBypassFECEncoder_i,
bypassScrambler_i => uplinkBypassScrambler_i,
-- Transceiver control
mgt_bitslipCtrl_o => mgt_rxslide_s,
-- Status
dataCorrected_o => open,
IcCorrected_o => open,
EcCorrected_o => open,
rdy_o => uplinkReady_o
);
end behavioral;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
This diff is collapsed.
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2016.3 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="17" Path="D:/LpGBT-FPGA/lpgbt-fpga-kcu105/Vivado/lpgbt-fpga-kcu105.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ee7b1704ed96439f978269f23d8a0350"/>
<Option Name="Part" Val="xcku040-ffva1156-2-e"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="BoardPart" Val="xilinx.com:kcu105:part0:1.1"/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="IPOutputRepo" Val="$PPRDIR/../../lpgbt-fpga-kcu105 - no hptd for release/Vivado/lpgbt-fpga-kcu105.cache/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PPRDIR/lpgbt-fpga-kcu105.ip_user_files"/>
<Option Name="IPStaticSourceDir" Val="$PPRDIR/lpgbt-fpga-kcu105.ip_user_files/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="kcu105"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="21"/>
<Option Name="WTModelSimExportSim" Val="21"/>
<Option Name="WTQuestaExportSim" Val="21"/>
<Option Name="WTIesExportSim" Val="21"/>
<Option Name="WTVcsExportSim" Val="21"/>
<Option Name="WTRivieraExportSim" Val="21"/>
<Option Name="WTActivehdlExportSim" Val="21"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="64"/>
<Option Name="XSimTraceLimit" Val="65536"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../LpGBT-FPGA/lpgbtfpga_package.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/top_tb.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/lpgbt_downlinkGenerator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/lpgbtfpga_top.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/uplink_checker.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_4b_generator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_8b_checker.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_8b_generator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_2b_generator.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_32b_checker.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_4b_checker.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TestBench_hw/prbs/prbs7_16b_checker.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../Mgt/xlx_ku_mgt_ip_reset_synchronizer.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../Mgt/xlx_ku_mgt.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/fec_rsDecoderN15K13.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/downlink/lpgbtfpga_encoder.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/lpgbtfpga_rxgearbox.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/lpgbtfpga_deinterleaver.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/descrambler_58bitOrder58.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/lpgbtfpga_descrambler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/downlink/rs_encoder_N7K5.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/descrambler_53bitOrder49.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/downlink/lpgbtfpga_scrambler.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/lpgbtfpga_uplink.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/lpgbtfpga_framealigner.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/lpgbtfpga_decoder.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/downlink/lpgbtfpga_interleaver.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/descrambler_60bitOrder58.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/fec_rsDecoderN31K29.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/lpbgtfpga_downlink.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/uplink/descrambler_51bitOrder49.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../LpGBT-FPGA/downlink/lpgbtfpga_txgearbox.vhd">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="lpgbt_fpga_kcu105"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../Constraints/kcu105_clks.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../Constraints/kcu105_io.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="lpgbt_fpga_kcu105"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="xlx_ku_mgt_ip" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xlx_ku_mgt_ip">
<File Path="$PPRDIR/../Mgt/xlx_ku_mgt_ip.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
<CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip.xci" FileRelPathName="synth/xlx_ku_mgt_ip.xdc">
<Attr Name="UserDisabled" Val="1"/>
<Attr Name="UsedInSynthesis" Val="0"/>
<Attr Name="UsedInImplementation" Val="0"/>
</CompFileExtendedInfo>
</File>
<Config>
<Option Name="TopModule" Val="xlx_ku_mgt_ip"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="vio_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/vio_0">
<File Path="$PSRCDIR/sources_1/ip/vio_0/vio_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="vio_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="10">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xcku040-ffva1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="xlx_ku_mgt_ip_synth_1" Type="Ft3:Synth" SrcSet="xlx_ku_mgt_ip" Part="xcku040-ffva1156-2-e" ConstrsSet="xlx_ku_mgt_ip" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xlx_ku_mgt_ip_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="vio_0_synth_1" Type="Ft3:Synth" SrcSet="vio_0" Part="xcku040-ffva1156-2-e" ConstrsSet="vio_0" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/vio_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="xlx_ku_mgt_ip_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-e" ConstrsSet="xlx_ku_mgt_ip" Description="Default settings for Implementation." SynthRun="xlx_ku_mgt_ip_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
<Run Id="vio_0_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-e" ConstrsSet="vio_0" Description="Default settings for Implementation." SynthRun="vio_0_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
</Run>
</Runs>
</Project>
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment