diff --git a/README.md b/README.md
index 7605ab5b3cbed52c2c4e335f4873e9d3155f35d0..24f26294c4a652acf9b1e66fcc6ad7a9ea1014f4 100644
--- a/README.md
+++ b/README.md
@@ -41,7 +41,7 @@ The vivado folder includes two projects:
> **Tip:** By default, the design are configured to work in FEC5 mode. To compile it for FEC12, you have to change the value of the FEC generic in the `lpgbtfpga_kcu105_10g24_top` or `lpgbtfpga_kcu105_5g12_top` file to `FEC12`.
-> **Tip:** Before using the example designs, the users have to update the GBT-SC submodule using the following terminal commands:
+> **Tip:** Before using the example designs, the users have to update the lpgbt-fpga submodule using the following terminal commands:
> ```
> cd lpgbt-fpga
> git submodule init
diff --git a/Vivado/lpgbt-fpga-kcu105-10g24.xpr b/Vivado/lpgbt-fpga-kcu105-10g24.xpr
index 87d72a0c23f157dc93509dbae394568088150dc6..473fdfeac228460b5ba28be9f613c946b64b379e 100644
--- a/Vivado/lpgbt-fpga-kcu105-10g24.xpr
+++ b/Vivado/lpgbt-fpga-kcu105-10g24.xpr
@@ -301,34 +301,6 @@
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="xlx_ku_mgt_ip_10g24_stub.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="xlx_ku_mgt_ip_10g24_sim_netlist.vhdl"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="xlx_ku_mgt_ip_10g24_sim_netlist.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="xlx_ku_mgt_ip_10g24_stub.vhdl"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtye4_cpll_cal.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_bit_sync.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/xlx_ku_mgt_ip_10g24_gtwizard_top.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/gtwizard_ultrascale_v1_6_gthe3_channel.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/xlx_ku_mgt_ip_10g24_gtwizard_gthe3.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_userclk_rx.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gthe4_cal_freqcnt.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gthe3_cal_freqcnt.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gthe3_cpll_cal.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/xlx_ku_mgt_ip_10g24.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/xlx_ku_mgt_ip_10g24_gthe3_channel_wrapper.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_reset_inv_sync.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_userdata_tx.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_userdata_rx.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_userclk_tx.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_reset.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_buffbypass_tx.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_reset_sync.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtye4_cal_freqcnt.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gtwiz_buffbypass_rx.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="hdl/gtwizard_ultrascale_v1_6_gthe4_cpll_cal.v"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/xlx_ku_mgt_ip_10g24_ooc.xdc"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="synth/xlx_ku_mgt_ip_10g24.xdc"/>
- <CompFileExtendedInfo CompFileName="xlx_ku_mgt_ip_10g24.xci" FileRelPathName="xlx_ku_mgt_ip_10g24.xml"/>
</File>
<Config>
<Option Name="TopModule" Val="xlx_ku_mgt_ip_10g24"/>
@@ -373,9 +345,7 @@
</Run>
<Run Id="xlx_ku_mgt_ip_10g24_synth_1" Type="Ft3:Synth" SrcSet="xlx_ku_mgt_ip_10g24" Part="xcku040-ffva1156-2-e" ConstrsSet="xlx_ku_mgt_ip_10g24" Description="Vivado Synthesis Defaults" Dir="$PRUNDIR/xlx_ku_mgt_ip_10g24_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016">
- <Desc>Vivado Synthesis Defaults</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2016"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -414,9 +384,7 @@
</Run>
<Run Id="xlx_ku_mgt_ip_10g24_impl_1" Type="Ft2:EntireDesign" Part="xcku040-ffva1156-2-e" ConstrsSet="xlx_ku_mgt_ip_10g24" Description="Default settings for Implementation." SynthRun="xlx_ku_mgt_ip_10g24_synth_1" IncludeInArchive="false">
<Strategy Version="1" Minor="2">
- <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016">
- <Desc>Default settings for Implementation.</Desc>
- </StratHandle>
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2016"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
diff --git a/constraints/kcu105_clks.xdc b/constraints/kcu105_clks.xdc
index 97064aac47e7f906ba9d5e7a6348d4c22bf2a265..8a18ce688a8029576f28e07b53176ce1b12dec40 100644
--- a/constraints/kcu105_clks.xdc
+++ b/constraints/kcu105_clks.xdc
@@ -36,11 +36,11 @@ create_clock -period 3.125 -name SMA_MGT_REFCLK [get_ports SMA_MGT_REFCLK_P]
# Multicycle constraints: ease the timing constraints
# Uplink constraints: Values depend on the c_multicyleDelay. Shall be the same one for setup time and -1 for the hold time
-set_multicycle_path 3 -from [get_pins {lpgbtFpga_top_inst/uplink_inst/frame_pipelined_s_reg[*]/C}] -setup
-set_multicycle_path 2 -from [get_pins {lpgbtFpga_top_inst/uplink_inst/frame_pipelined_s_reg[*]/C}] -hold
-set_multicycle_path 3 -from [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/uplink_inst/*descrambledData_reg[*]/C}] -setup
-set_multicycle_path 2 -from [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/uplink_inst/*descrambledData_reg[*]/C}] -hold
+set_multicycle_path 3 -from [get_pins {lpgbtFpga_inst/uplink_inst/frame_pipelined_s_reg[*]/C}] -setup
+set_multicycle_path 2 -from [get_pins {lpgbtFpga_inst/uplink_inst/frame_pipelined_s_reg[*]/C}] -hold
+set_multicycle_path 3 -from [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_inst/uplink_inst/*descrambledData_reg[*]/C}] -setup
+set_multicycle_path 2 -from [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_inst/uplink_inst/*descrambledData_reg[*]/C}] -hold
# Downlink constraints: Values depend on the c_multicyleDelay. Shall be the same one for setup time and -1 for the hold time
-set_multicycle_path -setup -to [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/downlink_inst/lpgbtfpga_scrambler_inst/scrambledData*/D}] 3
-set_multicycle_path -hold -to [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_top_inst/downlink_inst/lpgbtfpga_scrambler_inst/scrambledData*/D}] 2
\ No newline at end of file
+set_multicycle_path -setup -to [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_inst/downlink_inst/lpgbtfpga_scrambler_inst/scrambledData*/D}] 3
+set_multicycle_path -hold -to [get_pins -hierarchical -filter {NAME =~ lpgbtFpga_inst/downlink_inst/lpgbtfpga_scrambler_inst/scrambledData*/D}] 2
\ No newline at end of file
diff --git a/hdl/lpgbtfpga_10g24.vhd b/hdl/lpgbtfpga_10g24.vhd
index 69da35f166bab845ca45d9404bcee6276b454e76..9771ffbe0d8f794bd3b6836658d453717b553adc 100644
--- a/hdl/lpgbtfpga_10g24.vhd
+++ b/hdl/lpgbtfpga_10g24.vhd
@@ -1,38 +1,38 @@
-------------------------------------------------------
--! @file
---! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
+--! @author Julian MENDez <julian.mENDez@cern.ch> (CERN - EP-ESE-BE)
--! @version 2.0
---! @brief LpGBT-FPGA Top
+--! @brief LpGBT-FPGA Top - 10.24Gbps
-------------------------------------------------------
---! Include the IEEE VHDL standard library
-library ieee;
-use ieee.std_logic_1164.all;
+--! Include the IEEE VHDL standard LIBRARY
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
---! Include the LpGBT-FPGA specific package
-use work.lpgbtfpga_package.all;
+--! Include the LpGBT-FPGA specIFic package
+USE work.lpgbtfpga_package.all;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vCOMPONENTs.all;
-entity lpgbtFpga_10g24 is
+ENTITY lpgbtFpga_10g24 IS
GENERIC (
FEC : integer range 0 to 2 --! FEC selection can be: FEC5 or FEC12
);
PORT (
-- Clocks
donwlinkClk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
- downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
+ downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 WHEN encoding runs @ 320Mhz, '1' @ 40MHz)
uplinkClk_o : out std_logic; --! Clock provided by the Rx serdes: in phase with data
- uplinkClkEn_o : out std_logic; --! Clock enable pulsed when new data is ready
+ uplinkClkEn_o : out std_logic; --! Clock enable pulsed WHEN new data is ready
downlinkRst_i : in std_logic; --! Reset the downlink path
uplinkRst_i : in std_logic; --! Reset the uplink path
-- Down link
- downlinkUserData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
+ downlinkUSErData_i : in std_logic_vector(31 downto 0); --! Downlink data (USEr)
downlinkEcData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
downlinkIcData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
@@ -43,7 +43,7 @@ entity lpgbtFpga_10g24 is
downlinkReady_o : out std_logic; --! Downlink ready status
-- Up link
- uplinkUserData_o : out std_logic_vector(229 downto 0); --! Uplink data (user)
+ uplinkUSErData_o : out std_logic_vector(229 downto 0); --! Uplink data (USEr)
uplinkEcData_o : out std_logic_vector(1 downto 0); --! Uplink EC field
uplinkIcData_o : out std_logic_vector(1 downto 0); --! Uplink IC field
@@ -70,16 +70,16 @@ entity lpgbtFpga_10g24 is
mgt_txaligned_o : out std_logic;
mgt_txphase_o : out std_logic_vector(6 downto 0)
);
-end lpgbtFpga_10g24;
+END lpgbtFpga_10g24;
--=================================================================================================--
---#################################### Architecture ###########################################--
+--#################################### ARCHITECTURE ###########################################--
--=================================================================================================--
-architecture behavioral of lpgbtFpga_10g24 is
+ARCHITECTURE behavioral OF lpgbtFpga_10g24 IS
COMPONENT xlx_ku_mgt_10g24
- port (
+ PORT (
--=============--
-- Clocks --
--=============--
@@ -135,19 +135,19 @@ architecture behavioral of lpgbtFpga_10g24 is
c_clockRatio : integer := 8; --! Clock ratio is clock_out / 40 (shall be an integer - E.g.: 320/40 = 8)
c_outputWidth : integer --! Transceiver's word size
);
- port (
+ PORT (
-- Clocks
clk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
- clkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
- rst_n_i : in std_logic; --! Downlink reset signal (Tx ready from the transceiver)
+ clkEn_i : in std_logic; --! Clock enable (1 over 8 WHEN encoding runs @ 320Mhz, '1' @ 40MHz)
+ rst_n_i : in std_logic; --! Downlink reset SIGNAL (Tx ready from the transceiver)
-- Down link
- userData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
+ USErData_i : in std_logic_vector(31 downto 0); --! Downlink data (USEr)
ECData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
ICData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
-- Output
- mgt_word_o : out std_logic_vector((c_outputWidth-1) downto 0); --! Downlink encoded frame (IC + EC + User Data + FEC)
+ mgt_word_o : out std_logic_vector((c_outputWidth-1) downto 0); --! Downlink encoded frame (IC + EC + USEr Data + FEC)
-- Configuration
interleaverBypass_i : in std_logic; --! Bypass downlink interleaver (test purpose only)
@@ -167,26 +167,26 @@ architecture behavioral of lpgbtFpga_10g24 is
-- Expert parameters
c_multicyleDelay : integer range 0 to 7 := 3; --! Multicycle delay
- c_clockRatio : integer; --! Clock ratio is mgt_userclk / 40 (shall be an integer)
+ c_clockRatio : integer; --! Clock ratio is mgt_USErclk / 40 (shall be an integer)
c_mgtWordWidth : integer; --! Bus size of the input word
c_allowedFalseHeader : integer; --! Number of false header allowed to avoid unlock on frame error
c_allowedFalseHeaderOverN : integer; --! Number of header checked to know wether the lock is lost or not
c_requiredTrueHeader : integer; --! Number of true header required to go in locked state
- c_bitslip_mindly : integer := 1; --! Number of clock cycle required when asserting the bitslip signal
- c_bitslip_waitdly : integer := 40 --! Number of clock cycle required before being back in a stable state
+ c_bitslip_mindly : integer := 1; --! Number of clock cycle required WHEN asserting the bitslip SIGNAL
+ c_bitslip_waitdly : integer := 40 --! Number of clock cycle required beFORe being back in a stable state
);
PORT (
-- Clock and reset
clk_freeRunningClk_i : in std_logic;
- uplinkClk_i : in std_logic; --! Input clock (Rx user clock from transceiver)
- uplinkClkOutEn_o : out std_logic; --! Clock enable to be used in the user's logic
- uplinkRst_n_i : in std_logic; --! Uplink reset signal (Rx ready from the transceiver)
+ uplinkClk_i : in std_logic; --! Input clock (Rx USEr clock from transceiver)
+ uplinkClkOutEn_o : out std_logic; --! Clock enable to be USEd in the USEr's logic
+ uplinkRst_n_i : in std_logic; --! Uplink reset SIGNAL (Rx ready from the transceiver)
-- Input
mgt_word_o : in std_logic_vector((c_mgtWordWidth-1) downto 0); --! Input frame coming from the MGT
-- Data
- userData_o : out std_logic_vector(229 downto 0); --! User output (decoded data). The payload size varies depending on the
+ USErData_o : out std_logic_vector(229 downto 0); --! USEr output (decoded data). The payload size varies depENDing on the
--! datarate/FEC configuration:
--! * *FEC5 / 5.12 Gbps*: 112bit
--! * *FEC12 / 5.12 Gbps*: 98bit
@@ -201,24 +201,24 @@ architecture behavioral of lpgbtFpga_10g24 is
bypassScrambler_i : in std_logic; --! Bypass uplink scrambler (test purpose only)
-- Transceiver control
- mgt_bitslipCtrl_o : out std_logic; --! Control the Bitslib/RxSlide port of the Mgt
+ mgt_bitslipCtrl_o : out std_logic; --! Control the Bitslib/RxSlide PORT of the Mgt
-- Status
dataCorrected_o : out std_logic_vector(229 downto 0); --! Flag allowing to know which bit(s) were toggled by the FEC
IcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the IC field were toggled by the FEC
EcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the EC field were toggled by the FEC
- rdy_o : out std_logic --! Ready signal from the uplink decoder
+ rdy_o : out std_logic --! Ready SIGNAL from the uplink decoder
);
END COMPONENT;
- signal downlink_mgtword_s : std_logic_vector(31 downto 0);
- signal uplink_mgtword_s : std_logic_vector(31 downto 0);
- signal mgt_rxslide_s : std_logic;
- signal mgt_txrdy_s : std_logic;
- signal mgt_rxrdy_s : std_logic;
- signal clk_mgtRxClk_s : std_logic;
+ SIGNAL downlink_mgtword_s : std_logic_vector(31 downto 0);
+ SIGNAL uplink_mgtword_s : std_logic_vector(31 downto 0);
+ SIGNAL mgt_rxslide_s : std_logic;
+ SIGNAL mgt_txrdy_s : std_logic;
+ SIGNAL mgt_rxrdy_s : std_logic;
+ SIGNAL clk_mgtRxClk_s : std_logic;
-begin --========#### Architecture Body ####========--
+BEGIN --========#### ARCHITECTURE Body ####========--
downlink_inst: lpgbtfpga_Downlink
GENERIC MAP(
@@ -234,7 +234,7 @@ begin --========#### Architecture Body ####========--
rst_n_i => mgt_txrdy_s,
-- Down link
- userData_i => downlinkUserData_i,
+ USErData_i => downlinkUSErData_i,
ECData_i => downlinkEcData_i,
ICData_i => downlinkIcData_i,
@@ -251,7 +251,7 @@ begin --========#### Architecture Body ####========--
);
mgt_inst: xlx_ku_mgt_10g24
- port map(
+ PORT MAP(
--=============--
-- Clocks --
--=============--
@@ -273,7 +273,7 @@ begin --========#### Architecture Body ####========--
MGT_RXSlide_i => mgt_rxslide_s,
MGT_ENTXCALIBIN_i => '0',
- MGT_TXCALIB_i => (others => '0'),
+ MGT_TXCALIB_i => (OTHERS => '0'),
--=============--
-- Status --
@@ -329,7 +329,7 @@ begin --========#### Architecture Body ####========--
mgt_word_o => uplink_mgtword_s,
-- Data
- userData_o => uplinkUserData_o,
+ USErData_o => uplinkUSErData_o,
EcData_o => uplinkEcData_o,
IcData_o => uplinkIcData_o,
@@ -347,7 +347,7 @@ begin --========#### Architecture Body ####========--
EcCorrected_o => open,
rdy_o => uplinkReady_o
);
-end behavioral;
+END behavioral;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
diff --git a/hdl/lpgbtfpga_5g12.vhd b/hdl/lpgbtfpga_5g12.vhd
index eec24adeb3c00339a5df25d8096b451dd3142b73..47ff5f60552ab59a7f0a508cfb8cc2f76067ecf9 100644
--- a/hdl/lpgbtfpga_5g12.vhd
+++ b/hdl/lpgbtfpga_5g12.vhd
@@ -1,38 +1,38 @@
-------------------------------------------------------
--! @file
---! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
+--! @author Julian MENDez <julian.mENDez@cern.ch> (CERN - EP-ESE-BE)
--! @version 2.0
---! @brief LpGBT-FPGA Top
+--! @brief LpGBT-FPGA Top - 5.12Gbps
-------------------------------------------------------
---! Include the IEEE VHDL standard library
-library ieee;
-use ieee.std_logic_1164.all;
+--! Include the IEEE VHDL standard LIBRARY
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
---! Include the LpGBT-FPGA specific package
-use work.lpgbtfpga_package.all;
+--! Include the LpGBT-FPGA specIFic package
+USE work.lpgbtfpga_package.all;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vCOMPONENTs.all;
-entity lpgbtFpga_5g12 is
+ENTITY lpgbtFpga_5g12 IS
GENERIC (
FEC : integer range 0 to 2 --! FEC selection can be: FEC5 or FEC12
);
PORT (
-- Clocks
donwlinkClk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
- downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
+ downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 WHEN encoding runs @ 320Mhz, '1' @ 40MHz)
uplinkClk_o : out std_logic; --! Clock provided by the Rx serdes: in phase with data
- uplinkClkEn_o : out std_logic; --! Clock enable pulsed when new data is ready
+ uplinkClkEn_o : out std_logic; --! Clock enable pulsed WHEN new data is ready
downlinkRst_i : in std_logic; --! Reset the downlink path
uplinkRst_i : in std_logic; --! Reset the uplink path
-- Down link
- downlinkUserData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
+ downlinkUSErData_i : in std_logic_vector(31 downto 0); --! Downlink data (USEr)
downlinkEcData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
downlinkIcData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
@@ -43,7 +43,7 @@ entity lpgbtFpga_5g12 is
downlinkReady_o : out std_logic; --! Downlink ready status
-- Up link
- uplinkUserData_o : out std_logic_vector(229 downto 0); --! Uplink data (user)
+ uplinkUSErData_o : out std_logic_vector(229 downto 0); --! Uplink data (USEr)
uplinkEcData_o : out std_logic_vector(1 downto 0); --! Uplink EC field
uplinkIcData_o : out std_logic_vector(1 downto 0); --! Uplink IC field
@@ -70,16 +70,16 @@ entity lpgbtFpga_5g12 is
mgt_txaligned_o : out std_logic;
mgt_txphase_o : out std_logic_vector(6 downto 0)
);
-end lpgbtFpga_5g12;
+END lpgbtFpga_5g12;
--=================================================================================================--
---#################################### Architecture ###########################################--
+--#################################### ARCHITECTURE ###########################################--
--=================================================================================================--
-architecture behavioral of lpgbtFpga_5g12 is
+ARCHITECTURE behavioral OF lpgbtFpga_5g12 IS
COMPONENT xlx_ku_mgt_5g12
- port (
+ PORT (
--=============--
-- Clocks --
--=============--
@@ -135,19 +135,19 @@ architecture behavioral of lpgbtFpga_5g12 is
c_clockRatio : integer := 8; --! Clock ratio is clock_out / 40 (shall be an integer - E.g.: 320/40 = 8)
c_outputWidth : integer --! Transceiver's word size
);
- port (
+ PORT (
-- Clocks
clk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
- clkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
- rst_n_i : in std_logic; --! Downlink reset signal (Tx ready from the transceiver)
+ clkEn_i : in std_logic; --! Clock enable (1 over 8 WHEN encoding runs @ 320Mhz, '1' @ 40MHz)
+ rst_n_i : in std_logic; --! Downlink reset SIGNAL (Tx ready from the transceiver)
-- Down link
- userData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
+ USErData_i : in std_logic_vector(31 downto 0); --! Downlink data (USEr)
ECData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
ICData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
-- Output
- mgt_word_o : out std_logic_vector((c_outputWidth-1) downto 0); --! Downlink encoded frame (IC + EC + User Data + FEC)
+ mgt_word_o : out std_logic_vector((c_outputWidth-1) downto 0); --! Downlink encoded frame (IC + EC + USEr Data + FEC)
-- Configuration
interleaverBypass_i : in std_logic; --! Bypass downlink interleaver (test purpose only)
@@ -167,26 +167,26 @@ architecture behavioral of lpgbtFpga_5g12 is
-- Expert parameters
c_multicyleDelay : integer range 0 to 7 := 3; --! Multicycle delay
- c_clockRatio : integer; --! Clock ratio is mgt_userclk / 40 (shall be an integer)
+ c_clockRatio : integer; --! Clock ratio is mgt_USErclk / 40 (shall be an integer)
c_mgtWordWidth : integer; --! Bus size of the input word
c_allowedFalseHeader : integer; --! Number of false header allowed to avoid unlock on frame error
c_allowedFalseHeaderOverN : integer; --! Number of header checked to know wether the lock is lost or not
c_requiredTrueHeader : integer; --! Number of true header required to go in locked state
- c_bitslip_mindly : integer := 1; --! Number of clock cycle required when asserting the bitslip signal
- c_bitslip_waitdly : integer := 40 --! Number of clock cycle required before being back in a stable state
+ c_bitslip_mindly : integer := 1; --! Number of clock cycle required WHEN asserting the bitslip SIGNAL
+ c_bitslip_waitdly : integer := 40 --! Number of clock cycle required beFORe being back in a stable state
);
PORT (
-- Clock and reset
clk_freeRunningClk_i : in std_logic;
- uplinkClk_i : in std_logic; --! Input clock (Rx user clock from transceiver)
- uplinkClkOutEn_o : out std_logic; --! Clock enable to be used in the user's logic
- uplinkRst_n_i : in std_logic; --! Uplink reset signal (Rx ready from the transceiver)
+ uplinkClk_i : in std_logic; --! Input clock (Rx USEr clock from transceiver)
+ uplinkClkOutEn_o : out std_logic; --! Clock enable to be USEd in the USEr's logic
+ uplinkRst_n_i : in std_logic; --! Uplink reset SIGNAL (Rx ready from the transceiver)
-- Input
mgt_word_o : in std_logic_vector((c_mgtWordWidth-1) downto 0); --! Input frame coming from the MGT
-- Data
- userData_o : out std_logic_vector(229 downto 0); --! User output (decoded data). The payload size varies depending on the
+ USErData_o : out std_logic_vector(229 downto 0); --! USEr output (decoded data). The payload size varies depENDing on the
--! datarate/FEC configuration:
--! * *FEC5 / 5.12 Gbps*: 112bit
--! * *FEC12 / 5.12 Gbps*: 98bit
@@ -201,24 +201,24 @@ architecture behavioral of lpgbtFpga_5g12 is
bypassScrambler_i : in std_logic; --! Bypass uplink scrambler (test purpose only)
-- Transceiver control
- mgt_bitslipCtrl_o : out std_logic; --! Control the Bitslib/RxSlide port of the Mgt
+ mgt_bitslipCtrl_o : out std_logic; --! Control the Bitslib/RxSlide PORT of the Mgt
-- Status
dataCorrected_o : out std_logic_vector(229 downto 0); --! Flag allowing to know which bit(s) were toggled by the FEC
IcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the IC field were toggled by the FEC
EcCorrected_o : out std_logic_vector(1 downto 0); --! Flag allowing to know which bit(s) of the EC field were toggled by the FEC
- rdy_o : out std_logic --! Ready signal from the uplink decoder
+ rdy_o : out std_logic --! Ready SIGNAL from the uplink decoder
);
END COMPONENT;
- signal downlink_mgtword_s : std_logic_vector(15 downto 0);
- signal uplink_mgtword_s : std_logic_vector(15 downto 0);
- signal mgt_rxslide_s : std_logic;
- signal mgt_txrdy_s : std_logic;
- signal mgt_rxrdy_s : std_logic;
- signal clk_mgtRxClk_s : std_logic;
+ SIGNAL downlink_mgtword_s : std_logic_vector(15 downto 0);
+ SIGNAL uplink_mgtword_s : std_logic_vector(15 downto 0);
+ SIGNAL mgt_rxslide_s : std_logic;
+ SIGNAL mgt_txrdy_s : std_logic;
+ SIGNAL mgt_rxrdy_s : std_logic;
+ SIGNAL clk_mgtRxClk_s : std_logic;
-begin --========#### Architecture Body ####========--
+BEGIN --========#### ARCHITECTURE Body ####========--
downlink_inst: lpgbtfpga_Downlink
GENERIC MAP(
@@ -234,7 +234,7 @@ begin --========#### Architecture Body ####========--
rst_n_i => mgt_txrdy_s,
-- Down link
- userData_i => downlinkUserData_i,
+ USErData_i => downlinkUSErData_i,
ECData_i => downlinkEcData_i,
ICData_i => downlinkIcData_i,
@@ -251,7 +251,7 @@ begin --========#### Architecture Body ####========--
);
mgt_inst: xlx_ku_mgt_5g12
- port map(
+ PORT MAP(
--=============--
-- Clocks --
--=============--
@@ -273,7 +273,7 @@ begin --========#### Architecture Body ####========--
MGT_RXSlide_i => mgt_rxslide_s,
MGT_ENTXCALIBIN_i => '0',
- MGT_TXCALIB_i => (others => '0'),
+ MGT_TXCALIB_i => (OTHERS => '0'),
--=============--
-- Status --
@@ -329,7 +329,7 @@ begin --========#### Architecture Body ####========--
mgt_word_o => uplink_mgtword_s,
-- Data
- userData_o => uplinkUserData_o,
+ USErData_o => uplinkUSErData_o,
EcData_o => uplinkEcData_o,
IcData_o => uplinkIcData_o,
@@ -347,7 +347,7 @@ begin --========#### Architecture Body ####========--
EcCorrected_o => open,
rdy_o => uplinkReady_o
);
-end behavioral;
+END behavioral;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
diff --git a/hdl/lpgbtfpga_kcu105_10g24_top.vhd b/hdl/lpgbtfpga_kcu105_10g24_top.vhd
index 0d4e42a02c870cd66f72614ecdad16bcacd586ec..3e9858a0658478d55d0f50ccbe4874dcb089dd6a 100644
--- a/hdl/lpgbtfpga_kcu105_10g24_top.vhd
+++ b/hdl/lpgbtfpga_kcu105_10g24_top.vhd
@@ -1,33 +1,36 @@
-------------------------------------------------------
--! @file
---! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
+--! @author Julian MENDez <julian.mENDez@cern.ch> (CERN - EP-ESE-BE)
--! @version 2.0
--! @brief KCU105 Example design top - Includes VIOs and pattern gen/check.
+--! The Mgt and logic is configured to runs for a 10.24Gbps configuration
+--! but the FEC can be easily modified to FEC12 by changing the value of
+--! the lpgbtFpga_10g24's FEC generic.
-------------------------------------------------------
--- IEEE VHDL standard library:
-library ieee;
-use ieee.std_logic_1164.all;
+-- IEEE VHDL standard LIBRARY:
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
-package bus_multiplexer_pkg is
- type conf2b_array is array(natural range <>) of std_logic_vector(1 downto 0);
-end package;
+PACKAGE bus_multiplexer_pkg IS
+ TYPE conf2b_array is array(natural range <>) of std_logic_vector(1 downto 0);
+END PACKAGE;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vCOMPONENTs.all;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.bus_multiplexer_pkg.all;
-use work.lpgbtfpga_package.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.bus_multiplexer_pkg.all;
+USE work.lpgbtfpga_package.all;
--=================================================================================================--
---####################################### Entity ##############################################--
+--####################################### ENTITY ##############################################--
--=================================================================================================--
-entity lpgbtfpga_kcu105_10g24_top is
- port (
+ENTITY lpgbtfpga_kcu105_10g24_top IS
+ PORT (
--===============--
-- General reset --
--===============--
@@ -42,7 +45,7 @@ entity lpgbtfpga_kcu105_10g24_top is
-- Comment: * The MGT reference clock MUST be provided by an external clock generator.
--
- -- * The MGT reference clock frequency must be 120MHz for the latency-optimized GBT Bank.
+ -- * The MGT reference clock frequency must be 120MHz FOR the latency-optimized GBT Bank.
SMA_MGT_REFCLK_P : in std_logic;
SMA_MGT_REFCLK_N : in std_logic;
@@ -70,7 +73,7 @@ entity lpgbtfpga_kcu105_10g24_top is
SFP0_TX_DISABLE : out std_logic;
--====================--
- -- Signals forwarding --
+ -- SIGNALs FORwarding --
--====================--
-- SMA output:
@@ -78,32 +81,32 @@ entity lpgbtfpga_kcu105_10g24_top is
USER_SMA_GPIO_P : out std_logic;
USER_SMA_GPIO_N : out std_logic
);
-end lpgbtfpga_kcu105_10g24_top;
+END lpgbtfpga_kcu105_10g24_top;
--=================================================================================================--
---#################################### Architecture ###########################################--
+--#################################### ARCHITECTURE ###########################################--
--=================================================================================================--
-architecture behavioral of lpgbtfpga_kcu105_10g24_top is
+ARCHITECTURE behavioral OF lpgbtfpga_kcu105_10g24_top IS
- -- Components declaration
+ -- COMPONENTs declaration
COMPONENT lpgbtFpga_10g24
GENERIC (
- FEC : integer range 0 to 2 := FEC5 --! FEC selection can be: FEC5 or FEC12
+ FEC : integer range 0 to 2 --! FEC selection can be: FEC5 or FEC12
);
PORT (
-- Clocks
donwlinkClk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
- downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
+ downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 WHEN encoding runs @ 320Mhz, '1' @ 40MHz)
uplinkClk_o : out std_logic; --! Clock provided by the Rx serdes: in phase with data
- uplinkClkEn_o : out std_logic; --! Clock enable pulsed when new data is ready
+ uplinkClkEn_o : out std_logic; --! Clock enable pulsed WHEN new data is ready
downlinkRst_i : in std_logic; --! Reset the downlink path
uplinkRst_i : in std_logic; --! Reset the uplink path
-- Down link
- downlinkUserData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
+ downlinkUSErData_i : in std_logic_vector(31 downto 0); --! Downlink data (USEr)
downlinkEcData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
downlinkIcData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
@@ -114,7 +117,7 @@ architecture behavioral of lpgbtfpga_kcu105_10g24_top is
downlinkReady_o : out std_logic; --! Downlink ready status
-- Up link
- uplinkUserData_o : out std_logic_vector(229 downto 0); --! Uplink data (user)
+ uplinkUSErData_o : out std_logic_vector(229 downto 0); --! Uplink data (USEr)
uplinkEcData_o : out std_logic_vector(1 downto 0); --! Uplink EC field
uplinkIcData_o : out std_logic_vector(1 downto 0); --! Uplink IC field
@@ -200,9 +203,9 @@ architecture behavioral of lpgbtfpga_kcu105_10g24_top is
END COMPONENT;
COMPONENT lpgbtfpga_patterngen is
- port(
+ PORT(
clk320DnLink_i : in std_logic;
- clkEnDnLink_i : in std_logic;
+ clkENDnLink_i : in std_logic;
generator_rst_i : in std_logic;
@@ -215,12 +218,12 @@ architecture behavioral of lpgbtfpga_kcu105_10g24_top is
downlink_o : out std_logic_vector(31 downto 0);
- eport_gen_rdy_o : out std_logic_vector(15 downto 0)
+ ePORT_gen_rdy_o : out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT lpgbtfpga_patternchecker
- port (
+ PORT (
reset_checker_i : in std_logic;
ser320_clk_i : in std_logic;
ser320_clkEn_i : in std_logic;
@@ -231,118 +234,118 @@ architecture behavioral of lpgbtfpga_kcu105_10g24_top is
error_detected_o : out std_logic_vector(27 downto 0);
- userDataUpLink_i : in std_logic_vector(229 downto 0)
+ USErDataUpLink_i : in std_logic_vector(229 downto 0)
);
END COMPONENT;
- -- Signals:
+ -- SIGNALs:
-- Config
- signal uplinkSelectDataRate_s : std_logic := '0';
- signal uplinkSelectFEC_s : std_logic := '0';
+ SIGNAL uplinkSelectDataRate_s : std_logic := '0';
+ SIGNAL uplinkSelectFEC_s : std_logic := '0';
- signal downLinkBypassInterleaver_s : std_logic := '0';
- signal downLinkBypassFECEncoder_s : std_logic := '0';
- signal downLinkBypassScrambler_s : std_logic := '0';
+ SIGNAL downLinkBypassInterleaver_s : std_logic := '0';
+ SIGNAL downLinkBypassFECEncoder_s : std_logic := '0';
+ SIGNAL downLinkBypassScrambler_s : std_logic := '0';
- signal upLinkScramblerBypass_s : std_logic := '0';
- signal upLinkFecBypass_s : std_logic := '0';
- signal upLinkInterleaverBypass_s : std_logic := '0';
+ SIGNAL upLinkScramblerBypass_s : std_logic := '0';
+ SIGNAL upLinkFecBypass_s : std_logic := '0';
+ SIGNAL upLinkInterleaverBypass_s : std_logic := '0';
- signal reset_lpgbtfpga_from_jtag : std_logic := '0';
+ SIGNAL reset_lpgbtfpga_from_jtag : std_logic := '0';
-- Clocks:
- signal mgtRefClk_from_smaMgtRefClkbuf_s : std_logic;
- signal mgtRefClk_from_smaMgtRefClkbuf_img_s : std_logic;
- signal mgtRefClk_from_smaMgtRefClkbuf_img2_s : std_logic;
- signal mgt_freedrpclk_s : std_logic;
+ SIGNAL mgtRefClk_from_smaMgtRefClkbuf_s : std_logic;
+ SIGNAL mgtRefClk_from_smaMgtRefClkbuf_img_s : std_logic;
+ SIGNAL mgtRefClk_from_smaMgtRefClkbuf_img2_s : std_logic;
+ SIGNAL mgt_freedrpclk_s : std_logic;
- signal lpgbtfpga_mgttxclk_s : std_logic;
- signal lpgbtfpga_mgtrxclk_s : std_logic;
+ SIGNAL lpgbtfpga_mgttxclk_s : std_logic;
+ SIGNAL lpgbtfpga_mgtrxclk_s : std_logic;
- signal lpgbtfgpa_txclken_s : std_logic;
+ SIGNAL lpgbtfgpa_txclken_s : std_logic;
-- LpGBT-FPGA
- signal lpgbtfpga_downlinkrst_s : std_logic := '1';
- signal lpgbtfpga_downlinkrdy_s : std_logic;
- signal lpgbtfpga_uplinkrst_s : std_logic;
- signal lpgbtfpga_uplinkrdy_s : std_logic;
+ SIGNAL lpgbtfpga_downlinkrst_s : std_logic := '1';
+ SIGNAL lpgbtfpga_downlinkrdy_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkrst_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkrdy_s : std_logic;
- signal lpgbtfpga_downlinkUserData_s : std_logic_vector(31 downto 0);
- signal lpgbtfpga_downlinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_downlinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_downlinkUSErData_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtfpga_downlinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_downlinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_uplinkUserData_s : std_logic_vector(229 downto 0);
- signal lpgbtfpga_uplinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_uplinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_uplinkUSErData_s : std_logic_vector(229 downto 0);
+ SIGNAL lpgbtfpga_uplinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_uplinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_uplinkclk_s : std_logic;
- signal lpgbtfpga_uplinkclken_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkclk_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkclken_s : std_logic;
- signal uplinkErrorMaskInject_s : std_logic_vector(255 downto 0) := (others => '0');
- signal downlinkErrorMaskInject_s : std_logic_vector(63 downto 0) := (others => '0');
- signal downlink_forceHeaderErr_s : std_logic := '0';
- signal uplink_forceHeaderErr_s : std_logic := '0';
+ SIGNAL uplinkErrorMaskInject_s : std_logic_vector(255 downto 0) := (OTHERS => '0');
+ SIGNAL downlinkErrorMaskInject_s : std_logic_vector(63 downto 0) := (OTHERS => '0');
+ SIGNAL downlink_FORceHeaderErr_s : std_logic := '0';
+ SIGNAL uplink_FORceHeaderErr_s : std_logic := '0';
- signal lpgbtfpga_mgt_txaligned_s : std_logic;
- signal lpgbtfpga_mgt_txpiphase_s : std_logic_vector(6 downto 0);
- signal lpgbtfpga_mgt_txpicalib_s : std_logic_vector(6 downto 0);
- signal lpgbtfpga_mgt_txcaliben_s : std_logic;
+ SIGNAL lpgbtfpga_mgt_txaligned_s : std_logic;
+ SIGNAL lpgbtfpga_mgt_txpiphase_s : std_logic_vector(6 downto 0);
+ SIGNAL lpgbtfpga_mgt_txpicalib_s : std_logic_vector(6 downto 0);
+ SIGNAL lpgbtfpga_mgt_txcaliben_s : std_logic;
-- LpGBT-Emul
- signal lpgbtemul_uplinkrst_s : std_logic := '1';
- signal lpgbtemul_uplinkrdy_s : std_logic;
- signal lpgbtemul_downlinkrst_s : std_logic;
- signal lpgbtemul_downlinkrdy_s : std_logic;
+ SIGNAL lpgbtemul_uplinkrst_s : std_logic := '1';
+ SIGNAL lpgbtemul_uplinkrdy_s : std_logic;
+ SIGNAL lpgbtemul_downlinkrst_s : std_logic;
+ SIGNAL lpgbtemul_downlinkrdy_s : std_logic;
- signal lpgbtemul_downlinkUserData_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_downlinkUserData_g0_s : std_logic_vector(15 downto 0);
- signal lpgbtemul_downlinkUserData_g1_s : std_logic_vector(15 downto 0);
- signal lpgbtemul_downlinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_downlinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_downlinkUSErData_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_downlinkUSErData_g0_s : std_logic_vector(15 downto 0);
+ SIGNAL lpgbtemul_downlinkUSErData_g1_s : std_logic_vector(15 downto 0);
+ SIGNAL lpgbtemul_downlinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_downlinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_downlinkclk_s : std_logic;
- signal lpgbtemul_downlinkclken_s : std_logic;
- signal lpgbtemul_uplinkclk_s : std_logic;
- signal lpgbtemul_uplinkClkEn_s : std_logic;
+ SIGNAL lpgbtemul_downlinkclk_s : std_logic;
+ SIGNAL lpgbtemul_downlinkclken_s : std_logic;
+ SIGNAL lpgbtemul_uplinkclk_s : std_logic;
+ SIGNAL lpgbtemul_uplinkClkEn_s : std_logic;
- signal lpgbtemul_uplinkUserData_s : std_logic_vector(229 downto 0);
- signal lpgbtemul_uplinkUserData_g0_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g1_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g2_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g3_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g4_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g5_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g6_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_uplinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_s : std_logic_vector(229 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g0_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g1_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g2_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g3_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g4_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g5_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g6_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_uplinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_mgtRdy_s : std_logic;
+ SIGNAL lpgbtemul_mgtRdy_s : std_logic;
-- Serial
- signal downlinkSerial_s : std_logic;
- signal uplinkSerial_s : std_logic;
+ SIGNAL downlinkSerial_s : std_logic;
+ SIGNAL uplinkSerial_s : std_logic;
-- Gen / Checker
- signal uplink_error_s : std_logic;
- signal downlink_error_s : std_logic;
- signal downlink_txFlag_s : std_logic;
- signal downlink_rxFlag_s : std_logic;
- signal upLinkDataSel_s : std_logic;
+ SIGNAL uplink_error_s : std_logic;
+ SIGNAL downlink_error_s : std_logic;
+ SIGNAL downlink_txFlag_s : std_logic;
+ SIGNAL downlink_rxFlag_s : std_logic;
+ SIGNAL upLinkDataSel_s : std_logic;
- signal generator_rst_s : std_logic;
- signal downconfig_g0_s : std_logic_vector(1 downto 0);
- signal downconfig_g1_s : std_logic_vector(1 downto 0);
- signal downconfig_g2_s : std_logic_vector(1 downto 0);
- signal downconfig_g3_s : std_logic_vector(1 downto 0);
- signal downlink_gen_rdy_s : std_logic_vector(15 downto 0);
+ SIGNAL generator_rst_s : std_logic;
+ SIGNAL downconfig_g0_s : std_logic_vector(1 downto 0);
+ SIGNAL downconfig_g1_s : std_logic_vector(1 downto 0);
+ SIGNAL downconfig_g2_s : std_logic_vector(1 downto 0);
+ SIGNAL downconfig_g3_s : std_logic_vector(1 downto 0);
+ SIGNAL downlink_gen_rdy_s : std_logic_vector(15 downto 0);
- signal upelink_config_s : conf2b_array(27 downto 0);
- signal uperror_detected_s : std_logic_vector(27 downto 0);
- signal reset_upchecker_s : std_logic;
-begin --========#### Architecture Body ####========--
+ SIGNAL upelink_config_s : conf2b_array(27 downto 0);
+ SIGNAL uperror_detected_s : std_logic_vector(27 downto 0);
+ SIGNAL reset_upchecker_s : std_logic;
+BEGIN --========#### ARCHITECTURE Body ####========--
-- Reset controll
SFP0_TX_DISABLE <= '0';
@@ -352,14 +355,14 @@ begin --========#### Architecture Body ####========--
-- MGT(GTX) reference clock:
----------------------------
-- Comment: * The MGT reference clock MUST be provided by an external clock generator.
- -- * The MGT reference clock frequency must be 320MHz for the latency-optimized GBT Bank.
+ -- * The MGT reference clock frequency must be 320MHz FOR the latency-optimized GBT Bank.
smaMgtRefClkIbufdsGtxe2: ibufds_gte3
- generic map(
+ GENERIC MAP(
REFCLK_EN_TX_PATH => '0',
- REFCLK_HROW_CK_SEL => (others => '0'),
- REFCLK_ICNTL_RX => (others => '0')
+ REFCLK_HROW_CK_SEL => (OTHERS => '0'),
+ REFCLK_ICNTL_RX => (OTHERS => '0')
)
- port map (
+ PORT MAP (
O => mgtRefClk_from_smaMgtRefClkbuf_s,
ODIV2 => mgtRefClk_from_smaMgtRefClkbuf_img_s,
CEB => '0',
@@ -368,59 +371,59 @@ begin --========#### Architecture Body ####========--
);
mgtclk_img_bufg: BUFG_GT
- port map(
+ PORT MAP(
I => mgtRefClk_from_smaMgtRefClkbuf_img_s,
O => mgtRefClk_from_smaMgtRefClkbuf_img2_s,
CE => '1',
- DIV => (others => '0'),
+ DIV => (OTHERS => '0'),
CLR => '0',
CLRMASK => '0',
CEMASK => '0'
);
- userClockIbufgds: ibufgds
- generic map (
+ USErClockIbufgds: ibufgds
+ GENERIC MAP (
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "LVDS_25")
- port map (
+ PORT MAP (
O => mgt_freedrpclk_s,
I => USER_CLOCK_P,
IB => USER_CLOCK_N
);
- txClkEn_proc: process(lpgbtfpga_downlinkrst_s, lpgbtfpga_mgttxclk_s)
- variable cnter : integer range 0 to 8;
- begin
- if lpgbtfpga_downlinkrst_s = '1' then
+ txClkEn_proc: PROCESS(lpgbtfpga_downlinkrst_s, lpgbtfpga_mgttxclk_s)
+ VARIABLE cnter : integer range 0 to 8;
+ BEGIN
+ IF lpgbtfpga_downlinkrst_s = '1' THEN
cnter := 0;
lpgbtfgpa_txclken_s <= '0';
- elsif rising_edge(lpgbtfpga_mgttxclk_s) then
+ ELSIF rising_edge(lpgbtfpga_mgttxclk_s) THEN
cnter := cnter + 1;
- if cnter = 8 then
+ IF cnter = 8 THEN
cnter := 0;
- end if;
+ END IF;
lpgbtfgpa_txclken_s <= '0';
- if cnter = 0 then
+ IF cnter = 0 THEN
lpgbtfgpa_txclken_s <= '1';
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
-- Data stimulis
- lpgbtfpga_downlinkEcData_s <= (others => '1');
- lpgbtfpga_downlinkIcData_s <= (others => '1');
+ lpgbtfpga_downlinkEcData_s <= (OTHERS => '1');
+ lpgbtfpga_downlinkIcData_s <= (OTHERS => '1');
-- LpGBT FPGA
- lpgbtFpga_top_inst: lpgbtFpga_10g24
- generic map (
+ lpgbtFpga_inst: lpgbtFpga_10g24
+ GENERIC MAP (
FEC => FEC5
)
- port map (
+ PORT MAP (
-- Clocks
donwlinkClk_i => lpgbtfpga_mgttxclk_s,
downlinkClkEn_i => lpgbtfgpa_txclken_s,
@@ -432,7 +435,7 @@ begin --========#### Architecture Body ####========--
uplinkRst_i => lpgbtfpga_uplinkrst_s,
-- Down link
- downlinkUserData_i => lpgbtfpga_downlinkUserData_s,
+ downlinkUSErData_i => lpgbtfpga_downlinkUSErData_s,
downlinkEcData_i => lpgbtfpga_downlinkEcData_s,
downlinkIcData_i => lpgbtfpga_downlinkIcData_s,
@@ -443,7 +446,7 @@ begin --========#### Architecture Body ####========--
downlinkReady_o => lpgbtfpga_downlinkrdy_s,
-- Up link
- uplinkUserData_o => lpgbtfpga_uplinkUserData_s,
+ uplinkUSErData_o => lpgbtfpga_uplinkUSErData_s,
uplinkEcData_o => lpgbtfpga_uplinkEcData_s,
uplinkIcData_o => lpgbtfpga_uplinkIcData_s,
@@ -474,10 +477,10 @@ begin --========#### Architecture Body ####========--
-- Data pattern generator / checker (PRBS7)
lpgbtfpga_patterngen_inst: lpgbtfpga_patterngen
- port map(
+ PORT MAP(
--clk40Mhz_Tx_i : in std_logic;
clk320DnLink_i => lpgbtfpga_mgttxclk_s,
- clkEnDnLink_i => lpgbtfgpa_txclken_s,
+ clkENDnLink_i => lpgbtfgpa_txclken_s,
generator_rst_i => generator_rst_s,
@@ -491,15 +494,15 @@ begin --========#### Architecture Body ####========--
config_group2_i => downconfig_g2_s,
config_group3_i => downconfig_g3_s,
- downlink_o => lpgbtfpga_downlinkUserData_s,
+ downlink_o => lpgbtfpga_downlinkUSErData_s,
fixed_pattern_i => x"12345678",
- eport_gen_rdy_o => downlink_gen_rdy_s
+ ePORT_gen_rdy_o => downlink_gen_rdy_s
);
lpgbtfpga_patternchecker_inst: lpgbtfpga_patternchecker
- port map(
+ PORT MAP(
reset_checker_i => reset_upchecker_s,
ser320_clk_i => lpgbtfpga_uplinkclk_s,
ser320_clkEn_i => lpgbtfpga_uplinkclken_s,
@@ -510,7 +513,7 @@ begin --========#### Architecture Body ####========--
error_detected_o => uperror_detected_s,
- userDataUpLink_i => lpgbtfpga_uplinkUserData_s
+ USErDataUpLink_i => lpgbtfpga_uplinkUSErData_s
);
vio_debug_inst : vio_0
@@ -571,7 +574,7 @@ begin --========#### Architecture Body ####========--
USER_SMA_GPIO_P <= lpgbtfgpa_txclken_s;
USER_SMA_GPIO_N <= lpgbtfpga_mgttxclk_s;
-end behavioral;
+END behavioral;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
diff --git a/hdl/lpgbtfpga_kcu105_5g12_top.vhd b/hdl/lpgbtfpga_kcu105_5g12_top.vhd
index 5107d57d30f151c4f909cd767dd1832fd7947326..e564739cc0d50f5db899e13fcfcf7eb4910988a1 100644
--- a/hdl/lpgbtfpga_kcu105_5g12_top.vhd
+++ b/hdl/lpgbtfpga_kcu105_5g12_top.vhd
@@ -1,33 +1,36 @@
-------------------------------------------------------
--! @file
---! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
+--! @author Julian MENDez <julian.mENDez@cern.ch> (CERN - EP-ESE-BE)
--! @version 2.0
---! @brief KCU105 Example design top - Includes VIOs and pattern gen/check.
+--! @brief KCU105 Example design top - Includes VIOs and pattern gen/check
+--! The Mgt and logic is configured to runs for a 5.12Gbps configuration
+--! but the FEC can be easily modified to FEC12 by changing the value of
+--! the lpgbtFpga_5g12's FEC generic.
-------------------------------------------------------
--- IEEE VHDL standard library:
-library ieee;
-use ieee.std_logic_1164.all;
+-- IEEE VHDL standard LIBRARY:
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
-package bus_multiplexer_pkg is
- type conf2b_array is array(natural range <>) of std_logic_vector(1 downto 0);
-end package;
+PACKAGE bus_multiplexer_pkg IS
+ TYPE conf2b_array is array(natural range <>) of std_logic_vector(1 downto 0);
+END PACKAGE;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vCOMPONENTs.all;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.bus_multiplexer_pkg.all;
-use work.lpgbtfpga_package.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.bus_multiplexer_pkg.all;
+USE work.lpgbtfpga_package.all;
--=================================================================================================--
---####################################### Entity ##############################################--
+--####################################### ENTITY ##############################################--
--=================================================================================================--
-entity lpgbtfpga_kcu105_5g12_top is
- port (
+ENTITY lpgbtfpga_kcu105_5g12_top IS
+ PORT (
--===============--
-- General reset --
--===============--
@@ -42,7 +45,7 @@ entity lpgbtfpga_kcu105_5g12_top is
-- Comment: * The MGT reference clock MUST be provided by an external clock generator.
--
- -- * The MGT reference clock frequency must be 120MHz for the latency-optimized GBT Bank.
+ -- * The MGT reference clock frequency must be 120MHz FOR the latency-optimized GBT Bank.
SMA_MGT_REFCLK_P : in std_logic;
SMA_MGT_REFCLK_N : in std_logic;
@@ -70,7 +73,7 @@ entity lpgbtfpga_kcu105_5g12_top is
SFP0_TX_DISABLE : out std_logic;
--====================--
- -- Signals forwarding --
+ -- SIGNALs FORwarding --
--====================--
-- SMA output:
@@ -78,32 +81,32 @@ entity lpgbtfpga_kcu105_5g12_top is
USER_SMA_GPIO_P : out std_logic;
USER_SMA_GPIO_N : out std_logic
);
-end lpgbtfpga_kcu105_5g12_top;
+END lpgbtfpga_kcu105_5g12_top;
--=================================================================================================--
---#################################### Architecture ###########################################--
+--#################################### ARCHITECTURE ###########################################--
--=================================================================================================--
-architecture behavioral of lpgbtfpga_kcu105_5g12_top is
+ARCHITECTURE behavioral OF lpgbtfpga_kcu105_5g12_top IS
- -- Components declaration
+ -- COMPONENTs declaration
COMPONENT lpgbtFpga_5g12
GENERIC (
- FEC : integer range 0 to 2 := FEC5 --! FEC selection can be: FEC5 or FEC12
+ FEC : integer range 0 to 2 --! FEC selection can be: FEC5 or FEC12
);
PORT (
-- Clocks
donwlinkClk_i : in std_logic; --! Downlink datapath clock (either 320 or 40MHz)
- downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 when encoding runs @ 320Mhz, '1' @ 40MHz)
+ downlinkClkEn_i : in std_logic; --! Clock enable (1 over 8 WHEN encoding runs @ 320Mhz, '1' @ 40MHz)
uplinkClk_o : out std_logic; --! Clock provided by the Rx serdes: in phase with data
- uplinkClkEn_o : out std_logic; --! Clock enable pulsed when new data is ready
+ uplinkClkEn_o : out std_logic; --! Clock enable pulsed WHEN new data is ready
downlinkRst_i : in std_logic; --! Reset the downlink path
uplinkRst_i : in std_logic; --! Reset the uplink path
-- Down link
- downlinkUserData_i : in std_logic_vector(31 downto 0); --! Downlink data (user)
+ downlinkUSErData_i : in std_logic_vector(31 downto 0); --! Downlink data (USEr)
downlinkEcData_i : in std_logic_vector(1 downto 0); --! Downlink EC field
downlinkIcData_i : in std_logic_vector(1 downto 0); --! Downlink IC field
@@ -114,7 +117,7 @@ architecture behavioral of lpgbtfpga_kcu105_5g12_top is
downlinkReady_o : out std_logic; --! Downlink ready status
-- Up link
- uplinkUserData_o : out std_logic_vector(229 downto 0); --! Uplink data (user)
+ uplinkUSErData_o : out std_logic_vector(229 downto 0); --! Uplink data (USEr)
uplinkEcData_o : out std_logic_vector(1 downto 0); --! Uplink EC field
uplinkIcData_o : out std_logic_vector(1 downto 0); --! Uplink IC field
@@ -200,9 +203,9 @@ architecture behavioral of lpgbtfpga_kcu105_5g12_top is
END COMPONENT;
COMPONENT lpgbtfpga_patterngen is
- port(
+ PORT(
clk320DnLink_i : in std_logic;
- clkEnDnLink_i : in std_logic;
+ clkENDnLink_i : in std_logic;
generator_rst_i : in std_logic;
@@ -215,12 +218,12 @@ architecture behavioral of lpgbtfpga_kcu105_5g12_top is
downlink_o : out std_logic_vector(31 downto 0);
- eport_gen_rdy_o : out std_logic_vector(15 downto 0)
+ ePORT_gen_rdy_o : out std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT lpgbtfpga_patternchecker
- port (
+ PORT (
reset_checker_i : in std_logic;
ser320_clk_i : in std_logic;
ser320_clkEn_i : in std_logic;
@@ -231,118 +234,118 @@ architecture behavioral of lpgbtfpga_kcu105_5g12_top is
error_detected_o : out std_logic_vector(27 downto 0);
- userDataUpLink_i : in std_logic_vector(229 downto 0)
+ USErDataUpLink_i : in std_logic_vector(229 downto 0)
);
END COMPONENT;
- -- Signals:
+ -- SIGNALs:
-- Config
- signal uplinkSelectDataRate_s : std_logic := '0';
- signal uplinkSelectFEC_s : std_logic := '0';
+ SIGNAL uplinkSelectDataRate_s : std_logic := '0';
+ SIGNAL uplinkSelectFEC_s : std_logic := '0';
- signal downLinkBypassInterleaver_s : std_logic := '0';
- signal downLinkBypassFECEncoder_s : std_logic := '0';
- signal downLinkBypassScrambler_s : std_logic := '0';
+ SIGNAL downLinkBypassInterleaver_s : std_logic := '0';
+ SIGNAL downLinkBypassFECEncoder_s : std_logic := '0';
+ SIGNAL downLinkBypassScrambler_s : std_logic := '0';
- signal upLinkScramblerBypass_s : std_logic := '0';
- signal upLinkFecBypass_s : std_logic := '0';
- signal upLinkInterleaverBypass_s : std_logic := '0';
+ SIGNAL upLinkScramblerBypass_s : std_logic := '0';
+ SIGNAL upLinkFecBypass_s : std_logic := '0';
+ SIGNAL upLinkInterleaverBypass_s : std_logic := '0';
- signal reset_lpgbtfpga_from_jtag : std_logic := '0';
+ SIGNAL reset_lpgbtfpga_from_jtag : std_logic := '0';
-- Clocks:
- signal mgtRefClk_from_smaMgtRefClkbuf_s : std_logic;
- signal mgtRefClk_from_smaMgtRefClkbuf_img_s : std_logic;
- signal mgtRefClk_from_smaMgtRefClkbuf_img2_s : std_logic;
- signal mgt_freedrpclk_s : std_logic;
+ SIGNAL mgtRefClk_from_smaMgtRefClkbuf_s : std_logic;
+ SIGNAL mgtRefClk_from_smaMgtRefClkbuf_img_s : std_logic;
+ SIGNAL mgtRefClk_from_smaMgtRefClkbuf_img2_s : std_logic;
+ SIGNAL mgt_freedrpclk_s : std_logic;
- signal lpgbtfpga_mgttxclk_s : std_logic;
- signal lpgbtfpga_mgtrxclk_s : std_logic;
+ SIGNAL lpgbtfpga_mgttxclk_s : std_logic;
+ SIGNAL lpgbtfpga_mgtrxclk_s : std_logic;
- signal lpgbtfgpa_txclken_s : std_logic;
+ SIGNAL lpgbtfgpa_txclken_s : std_logic;
-- LpGBT-FPGA
- signal lpgbtfpga_downlinkrst_s : std_logic := '1';
- signal lpgbtfpga_downlinkrdy_s : std_logic;
- signal lpgbtfpga_uplinkrst_s : std_logic;
- signal lpgbtfpga_uplinkrdy_s : std_logic;
+ SIGNAL lpgbtfpga_downlinkrst_s : std_logic := '1';
+ SIGNAL lpgbtfpga_downlinkrdy_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkrst_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkrdy_s : std_logic;
- signal lpgbtfpga_downlinkUserData_s : std_logic_vector(31 downto 0);
- signal lpgbtfpga_downlinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_downlinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_downlinkUSErData_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtfpga_downlinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_downlinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_uplinkUserData_s : std_logic_vector(229 downto 0);
- signal lpgbtfpga_uplinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_uplinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_uplinkUSErData_s : std_logic_vector(229 downto 0);
+ SIGNAL lpgbtfpga_uplinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtfpga_uplinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtfpga_uplinkclk_s : std_logic;
- signal lpgbtfpga_uplinkclken_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkclk_s : std_logic;
+ SIGNAL lpgbtfpga_uplinkclken_s : std_logic;
- signal uplinkErrorMaskInject_s : std_logic_vector(255 downto 0) := (others => '0');
- signal downlinkErrorMaskInject_s : std_logic_vector(63 downto 0) := (others => '0');
- signal downlink_forceHeaderErr_s : std_logic := '0';
- signal uplink_forceHeaderErr_s : std_logic := '0';
+ SIGNAL uplinkErrorMaskInject_s : std_logic_vector(255 downto 0) := (OTHERS => '0');
+ SIGNAL downlinkErrorMaskInject_s : std_logic_vector(63 downto 0) := (OTHERS => '0');
+ SIGNAL downlink_FORceHeaderErr_s : std_logic := '0';
+ SIGNAL uplink_FORceHeaderErr_s : std_logic := '0';
- signal lpgbtfpga_mgt_txaligned_s : std_logic;
- signal lpgbtfpga_mgt_txpiphase_s : std_logic_vector(6 downto 0);
- signal lpgbtfpga_mgt_txpicalib_s : std_logic_vector(6 downto 0);
- signal lpgbtfpga_mgt_txcaliben_s : std_logic;
+ SIGNAL lpgbtfpga_mgt_txaligned_s : std_logic;
+ SIGNAL lpgbtfpga_mgt_txpiphase_s : std_logic_vector(6 downto 0);
+ SIGNAL lpgbtfpga_mgt_txpicalib_s : std_logic_vector(6 downto 0);
+ SIGNAL lpgbtfpga_mgt_txcaliben_s : std_logic;
-- LpGBT-Emul
- signal lpgbtemul_uplinkrst_s : std_logic := '1';
- signal lpgbtemul_uplinkrdy_s : std_logic;
- signal lpgbtemul_downlinkrst_s : std_logic;
- signal lpgbtemul_downlinkrdy_s : std_logic;
+ SIGNAL lpgbtemul_uplinkrst_s : std_logic := '1';
+ SIGNAL lpgbtemul_uplinkrdy_s : std_logic;
+ SIGNAL lpgbtemul_downlinkrst_s : std_logic;
+ SIGNAL lpgbtemul_downlinkrdy_s : std_logic;
- signal lpgbtemul_downlinkUserData_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_downlinkUserData_g0_s : std_logic_vector(15 downto 0);
- signal lpgbtemul_downlinkUserData_g1_s : std_logic_vector(15 downto 0);
- signal lpgbtemul_downlinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_downlinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_downlinkUSErData_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_downlinkUSErData_g0_s : std_logic_vector(15 downto 0);
+ SIGNAL lpgbtemul_downlinkUSErData_g1_s : std_logic_vector(15 downto 0);
+ SIGNAL lpgbtemul_downlinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_downlinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_downlinkclk_s : std_logic;
- signal lpgbtemul_downlinkclken_s : std_logic;
- signal lpgbtemul_uplinkclk_s : std_logic;
- signal lpgbtemul_uplinkClkEn_s : std_logic;
+ SIGNAL lpgbtemul_downlinkclk_s : std_logic;
+ SIGNAL lpgbtemul_downlinkclken_s : std_logic;
+ SIGNAL lpgbtemul_uplinkclk_s : std_logic;
+ SIGNAL lpgbtemul_uplinkClkEn_s : std_logic;
- signal lpgbtemul_uplinkUserData_s : std_logic_vector(229 downto 0);
- signal lpgbtemul_uplinkUserData_g0_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g1_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g2_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g3_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g4_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g5_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkUserData_g6_s : std_logic_vector(31 downto 0);
- signal lpgbtemul_uplinkIcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_uplinkEcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_s : std_logic_vector(229 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g0_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g1_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g2_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g3_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g4_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g5_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkUSErData_g6_s : std_logic_vector(31 downto 0);
+ SIGNAL lpgbtemul_uplinkIcData_s : std_logic_vector(1 downto 0);
+ SIGNAL lpgbtemul_uplinkEcData_s : std_logic_vector(1 downto 0);
- signal lpgbtemul_mgtRdy_s : std_logic;
+ SIGNAL lpgbtemul_mgtRdy_s : std_logic;
-- Serial
- signal downlinkSerial_s : std_logic;
- signal uplinkSerial_s : std_logic;
+ SIGNAL downlinkSerial_s : std_logic;
+ SIGNAL uplinkSerial_s : std_logic;
-- Gen / Checker
- signal uplink_error_s : std_logic;
- signal downlink_error_s : std_logic;
- signal downlink_txFlag_s : std_logic;
- signal downlink_rxFlag_s : std_logic;
- signal upLinkDataSel_s : std_logic;
+ SIGNAL uplink_error_s : std_logic;
+ SIGNAL downlink_error_s : std_logic;
+ SIGNAL downlink_txFlag_s : std_logic;
+ SIGNAL downlink_rxFlag_s : std_logic;
+ SIGNAL upLinkDataSel_s : std_logic;
- signal generator_rst_s : std_logic;
- signal downconfig_g0_s : std_logic_vector(1 downto 0);
- signal downconfig_g1_s : std_logic_vector(1 downto 0);
- signal downconfig_g2_s : std_logic_vector(1 downto 0);
- signal downconfig_g3_s : std_logic_vector(1 downto 0);
- signal downlink_gen_rdy_s : std_logic_vector(15 downto 0);
+ SIGNAL generator_rst_s : std_logic;
+ SIGNAL downconfig_g0_s : std_logic_vector(1 downto 0);
+ SIGNAL downconfig_g1_s : std_logic_vector(1 downto 0);
+ SIGNAL downconfig_g2_s : std_logic_vector(1 downto 0);
+ SIGNAL downconfig_g3_s : std_logic_vector(1 downto 0);
+ SIGNAL downlink_gen_rdy_s : std_logic_vector(15 downto 0);
- signal upelink_config_s : conf2b_array(27 downto 0);
- signal uperror_detected_s : std_logic_vector(27 downto 0);
- signal reset_upchecker_s : std_logic;
-begin --========#### Architecture Body ####========--
+ SIGNAL upelink_config_s : conf2b_array(27 downto 0);
+ SIGNAL uperror_detected_s : std_logic_vector(27 downto 0);
+ SIGNAL reset_upchecker_s : std_logic;
+BEGIN --========#### ARCHITECTURE Body ####========--
-- Reset controll
SFP0_TX_DISABLE <= '0';
@@ -352,14 +355,14 @@ begin --========#### Architecture Body ####========--
-- MGT(GTX) reference clock:
----------------------------
-- Comment: * The MGT reference clock MUST be provided by an external clock generator.
- -- * The MGT reference clock frequency must be 320MHz for the latency-optimized GBT Bank.
+ -- * The MGT reference clock frequency must be 320MHz FOR the latency-optimized GBT Bank.
smaMgtRefClkIbufdsGtxe2: ibufds_gte3
- generic map(
+ GENERIC MAP(
REFCLK_EN_TX_PATH => '0',
- REFCLK_HROW_CK_SEL => (others => '0'),
- REFCLK_ICNTL_RX => (others => '0')
+ REFCLK_HROW_CK_SEL => (OTHERS => '0'),
+ REFCLK_ICNTL_RX => (OTHERS => '0')
)
- port map (
+ PORT MAP (
O => mgtRefClk_from_smaMgtRefClkbuf_s,
ODIV2 => mgtRefClk_from_smaMgtRefClkbuf_img_s,
CEB => '0',
@@ -368,59 +371,59 @@ begin --========#### Architecture Body ####========--
);
mgtclk_img_bufg: BUFG_GT
- port map(
+ PORT MAP(
I => mgtRefClk_from_smaMgtRefClkbuf_img_s,
O => mgtRefClk_from_smaMgtRefClkbuf_img2_s,
CE => '1',
- DIV => (others => '0'),
+ DIV => (OTHERS => '0'),
CLR => '0',
CLRMASK => '0',
CEMASK => '0'
);
- userClockIbufgds: ibufgds
- generic map (
+ USErClockIbufgds: ibufgds
+ GENERIC MAP (
IBUF_LOW_PWR => FALSE,
IOSTANDARD => "LVDS_25")
- port map (
+ PORT MAP (
O => mgt_freedrpclk_s,
I => USER_CLOCK_P,
IB => USER_CLOCK_N
);
- txClkEn_proc: process(lpgbtfpga_downlinkrst_s, lpgbtfpga_mgttxclk_s)
- variable cnter : integer range 0 to 8;
- begin
- if lpgbtfpga_downlinkrst_s = '1' then
+ txClkEn_proc: PROCESS(lpgbtfpga_downlinkrst_s, lpgbtfpga_mgttxclk_s)
+ VARIABLE cnter : integer range 0 to 8;
+ BEGIN
+ IF lpgbtfpga_downlinkrst_s = '1' THEN
cnter := 0;
lpgbtfgpa_txclken_s <= '0';
- elsif rising_edge(lpgbtfpga_mgttxclk_s) then
+ ELSIF rising_edge(lpgbtfpga_mgttxclk_s) THEN
cnter := cnter + 1;
- if cnter = 8 then
+ IF cnter = 8 THEN
cnter := 0;
- end if;
+ END IF;
lpgbtfgpa_txclken_s <= '0';
- if cnter = 0 then
+ IF cnter = 0 THEN
lpgbtfgpa_txclken_s <= '1';
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
-- Data stimulis
- lpgbtfpga_downlinkEcData_s <= (others => '1');
- lpgbtfpga_downlinkIcData_s <= (others => '1');
+ lpgbtfpga_downlinkEcData_s <= (OTHERS => '1');
+ lpgbtfpga_downlinkIcData_s <= (OTHERS => '1');
-- LpGBT FPGA
- lpgbtFpga_top_inst: lpgbtFpga_5g12
- generic map (
+ lpgbtFpga_inst: lpgbtFpga_5g12
+ GENERIC MAP (
FEC => FEC5
)
- port map (
+ PORT MAP (
-- Clocks
donwlinkClk_i => lpgbtfpga_mgttxclk_s,
downlinkClkEn_i => lpgbtfgpa_txclken_s,
@@ -432,7 +435,7 @@ begin --========#### Architecture Body ####========--
uplinkRst_i => lpgbtfpga_uplinkrst_s,
-- Down link
- downlinkUserData_i => lpgbtfpga_downlinkUserData_s,
+ downlinkUSErData_i => lpgbtfpga_downlinkUSErData_s,
downlinkEcData_i => lpgbtfpga_downlinkEcData_s,
downlinkIcData_i => lpgbtfpga_downlinkIcData_s,
@@ -443,7 +446,7 @@ begin --========#### Architecture Body ####========--
downlinkReady_o => lpgbtfpga_downlinkrdy_s,
-- Up link
- uplinkUserData_o => lpgbtfpga_uplinkUserData_s,
+ uplinkUSErData_o => lpgbtfpga_uplinkUSErData_s,
uplinkEcData_o => lpgbtfpga_uplinkEcData_s,
uplinkIcData_o => lpgbtfpga_uplinkIcData_s,
@@ -474,10 +477,10 @@ begin --========#### Architecture Body ####========--
-- Data pattern generator / checker (PRBS7)
lpgbtfpga_patterngen_inst: lpgbtfpga_patterngen
- port map(
+ PORT MAP(
--clk40Mhz_Tx_i : in std_logic;
clk320DnLink_i => lpgbtfpga_mgttxclk_s,
- clkEnDnLink_i => lpgbtfgpa_txclken_s,
+ clkENDnLink_i => lpgbtfgpa_txclken_s,
generator_rst_i => generator_rst_s,
@@ -491,15 +494,15 @@ begin --========#### Architecture Body ####========--
config_group2_i => downconfig_g2_s,
config_group3_i => downconfig_g3_s,
- downlink_o => lpgbtfpga_downlinkUserData_s,
+ downlink_o => lpgbtfpga_downlinkUSErData_s,
fixed_pattern_i => x"12345678",
- eport_gen_rdy_o => downlink_gen_rdy_s
+ ePORT_gen_rdy_o => downlink_gen_rdy_s
);
lpgbtfpga_patternchecker_inst: lpgbtfpga_patternchecker
- port map(
+ PORT MAP(
reset_checker_i => reset_upchecker_s,
ser320_clk_i => lpgbtfpga_uplinkclk_s,
ser320_clkEn_i => lpgbtfpga_uplinkclken_s,
@@ -510,7 +513,7 @@ begin --========#### Architecture Body ####========--
error_detected_o => uperror_detected_s,
- userDataUpLink_i => lpgbtfpga_uplinkUserData_s
+ USErDataUpLink_i => lpgbtfpga_uplinkUSErData_s
);
vio_debug_inst : vio_0
@@ -571,7 +574,7 @@ begin --========#### Architecture Body ####========--
USER_SMA_GPIO_P <= lpgbtfgpa_txclken_s;
USER_SMA_GPIO_N <= lpgbtfpga_mgttxclk_s;
-end behavioral;
+END behavioral;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
diff --git a/hdl/lpgbtfpga_patternchecker.vhd b/hdl/lpgbtfpga_patternchecker.vhd
index 82a8a733dc86bb83709d4354e776648a9a1c1aa6..3895cc2e1912009da3ce553e3a5e5d70f3149036 100644
--- a/hdl/lpgbtfpga_patternchecker.vhd
+++ b/hdl/lpgbtfpga_patternchecker.vhd
@@ -1,22 +1,22 @@
--- IEEE VHDL standard library:
-library ieee;
-use ieee.std_logic_1164.all;
+-- IEEE VHDL standard LIBRARY:
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
-package bus_multiplexer_pkg is
- type conf2b_array is array(natural range <>) of std_logic_vector(1 downto 0);
-end package;
+PACKAGE bus_multiplexer_pkg IS
+ TYPE conf2b_array is array(natural range <>) of std_logic_vector(1 downto 0);
+END PACKAGE;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vCOMPONENTs.all;
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use work.bus_multiplexer_pkg.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+USE work.bus_multiplexer_pkg.all;
-entity lpgbtfpga_patternchecker is
- port (
+ENTITY lpgbtfpga_patternchecker IS
+ PORT (
reset_checker_i : in std_logic;
ser320_clk_i : in std_logic;
ser320_clkEn_i : in std_logic;
@@ -27,14 +27,14 @@ entity lpgbtfpga_patternchecker is
error_detected_o : out std_logic_vector(27 downto 0);
- userDataUpLink_i : in std_logic_vector(229 downto 0)
+ USErDataUpLink_i : in std_logic_vector(229 downto 0)
);
-end lpgbtfpga_patternchecker;
+END lpgbtfpga_patternchecker;
-architecture rtl of lpgbtfpga_patternchecker is
+ARCHITECTURE rtl of lpgbtfpga_patternchecker IS
- component prbs7_32b_checker
- port (
+ COMPONENT prbs7_32b_checker
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -42,10 +42,10 @@ architecture rtl of lpgbtfpga_patternchecker is
err_o : out std_logic_vector(31 downto 0);
rdy_o : out std_logic
);
- end component;
+ END COMPONENT;
- component prbs7_16b_checker
- port (
+ COMPONENT prbs7_16b_checker
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -53,10 +53,10 @@ architecture rtl of lpgbtfpga_patternchecker is
err_o : out std_logic_vector(15 downto 0);
rdy_o : out std_logic
);
- end component;
+ END COMPONENT;
- component prbs7_8b_checker
- port (
+ COMPONENT prbs7_8b_checker
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -64,10 +64,10 @@ architecture rtl of lpgbtfpga_patternchecker is
err_o : out std_logic_vector(7 downto 0);
rdy_o : out std_logic
);
- end component;
+ END COMPONENT;
- component prbs7_4b_checker
- port (
+ COMPONENT prbs7_4b_checker
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -75,134 +75,134 @@ architecture rtl of lpgbtfpga_patternchecker is
err_o : out std_logic_vector(3 downto 0);
rdy_o : out std_logic
);
- end component;
-
- type elink_1g28_T is array(integer range <>) of std_logic_vector(31 downto 0);
- type elink_640m_T is array(integer range <>) of std_logic_vector(15 downto 0);
- type elink_320m_T is array(integer range <>) of std_logic_vector(7 downto 0);
- type elink_160m_T is array(integer range <>) of std_logic_vector(3 downto 0);
- type bert_cnter_T is array(integer range <>) of std_logic_vector(63 downto 0);
- type err_cnter_T is array(integer range <>) of std_logic_vector(5 downto 0);
- type cnt_arr_T is array(integer range <>) of unsigned(31 downto 0);
-
- signal elink_1g28_s : elink_1g28_T(6 downto 0); -- Maximum of 7 links @ 1.28gbps
- signal elink_640m_s : elink_640m_T(14 downto 0); -- Maximum of 14 links @ 640Mbps
- signal elink_320m_s : elink_320m_T(27 downto 0); -- Maximum of 28 links @ 320Mbps
- signal elink_160m_s : elink_160m_T(27 downto 0); -- Maximum of 28 links @ 160Mbps
-
- signal elink_1g28_err_s : elink_1g28_T(27 downto 0);
- signal elink_640m_err_s : elink_640m_T(27 downto 0);
- signal elink_320m_err_s : elink_320m_T(27 downto 0);
- signal elink_160m_err_s : elink_160m_T(27 downto 0);
-
- signal elink_err_s : elink_1g28_T(27 downto 0);
- signal cntr_rst_s : std_logic_vector(27 downto 0);
- signal elink_prbs_rdy : std_logic_vector(27 downto 0);
-
- signal elink_1g28_prbsRdy_s : std_logic_vector(27 downto 0);
- signal elink_640m_prbsRdy_s : std_logic_vector(27 downto 0);
- signal elink_320m_prbsRdy_s : std_logic_vector(27 downto 0);
- signal elink_160m_prbsRdy_s : std_logic_vector(27 downto 0);
-
- signal reset320_s : std_logic;
- signal rst_dst_s : std_logic;
-begin
-
- reset_synch_proc: process(reset_checker_i, ser320_clk_i)
- begin
- if reset_checker_i = '1' then
+ END COMPONENT;
+
+ TYPE elink_1g28_T is array(integer range <>) of std_logic_vector(31 downto 0);
+ TYPE elink_640m_T is array(integer range <>) of std_logic_vector(15 downto 0);
+ TYPE elink_320m_T is array(integer range <>) of std_logic_vector(7 downto 0);
+ TYPE elink_160m_T is array(integer range <>) of std_logic_vector(3 downto 0);
+ TYPE bert_cnter_T is array(integer range <>) of std_logic_vector(63 downto 0);
+ TYPE err_cnter_T is array(integer range <>) of std_logic_vector(5 downto 0);
+ TYPE cnt_arr_T is array(integer range <>) of unsigned(31 downto 0);
+
+ SIGNAL elink_1g28_s : elink_1g28_T(6 downto 0); -- Maximum of 7 links @ 1.28gbps
+ SIGNAL elink_640m_s : elink_640m_T(14 downto 0); -- Maximum of 14 links @ 640Mbps
+ SIGNAL elink_320m_s : elink_320m_T(27 downto 0); -- Maximum of 28 links @ 320Mbps
+ SIGNAL elink_160m_s : elink_160m_T(27 downto 0); -- Maximum of 28 links @ 160Mbps
+
+ SIGNAL elink_1g28_err_s : elink_1g28_T(27 downto 0);
+ SIGNAL elink_640m_err_s : elink_640m_T(27 downto 0);
+ SIGNAL elink_320m_err_s : elink_320m_T(27 downto 0);
+ SIGNAL elink_160m_err_s : elink_160m_T(27 downto 0);
+
+ SIGNAL elink_err_s : elink_1g28_T(27 downto 0);
+ SIGNAL cntr_rst_s : std_logic_vector(27 downto 0);
+ SIGNAL elink_prbs_rdy : std_logic_vector(27 downto 0);
+
+ SIGNAL elink_1g28_prbsRdy_s : std_logic_vector(27 downto 0);
+ SIGNAL elink_640m_prbsRdy_s : std_logic_vector(27 downto 0);
+ SIGNAL elink_320m_prbsRdy_s : std_logic_vector(27 downto 0);
+ SIGNAL elink_160m_prbsRdy_s : std_logic_vector(27 downto 0);
+
+ SIGNAL reset320_s : std_logic;
+ SIGNAL rst_dst_s : std_logic;
+BEGIN
+
+ reset_synch_proc: PROCESS(reset_checker_i, ser320_clk_i)
+ BEGIN
+ IF reset_checker_i = '1' THEN
rst_dst_s <= '1';
reset320_s <= '1';
- elsif rising_edge(ser320_clk_i) then
+ ELSIF rising_edge(ser320_clk_i) THEN
rst_dst_s <= '0';
reset320_s <= rst_dst_s;
- end if;
- end process;
+ END IF;
+ END PROCESS;
- elink_1g28_s(0) <= userDataUpLink_i(31 downto 0);
- elink_1g28_s(1) <= userDataUpLink_i(63 downto 32);
- elink_1g28_s(2) <= userDataUpLink_i(95 downto 64);
- elink_1g28_s(3) <= userDataUpLink_i(127 downto 96);
- elink_1g28_s(4) <= userDataUpLink_i(159 downto 128);
- elink_1g28_s(5) <= userDataUpLink_i(191 downto 160);
- elink_1g28_s(6) <= userDataUpLink_i(223 downto 192);
-
- elink_640m_s(0) <= userDataUpLink_i(15 downto 0);
- elink_640m_s(1) <= userDataUpLink_i(31 downto 16) when data_rate_i = '1' else (others => '0');
- elink_640m_s(2) <= userDataUpLink_i(47 downto 32) when data_rate_i = '1' else userDataUpLink_i(31 downto 16);
- elink_640m_s(3) <= userDataUpLink_i(63 downto 48) when data_rate_i = '1' else (others => '0');
- elink_640m_s(4) <= userDataUpLink_i(79 downto 64) when data_rate_i = '1' else userDataUpLink_i(47 downto 32);
- elink_640m_s(5) <= userDataUpLink_i(95 downto 80) when data_rate_i = '1' else (others => '0');
- elink_640m_s(6) <= userDataUpLink_i(111 downto 96) when data_rate_i = '1' else userDataUpLink_i(63 downto 48);
- elink_640m_s(7) <= userDataUpLink_i(127 downto 112) when data_rate_i = '1' else (others => '0');
- elink_640m_s(8) <= userDataUpLink_i(143 downto 128) when data_rate_i = '1' else userDataUpLink_i(79 downto 64);
- elink_640m_s(9) <= userDataUpLink_i(159 downto 144) when data_rate_i = '1' else (others => '0');
- elink_640m_s(10) <= userDataUpLink_i(175 downto 160) when data_rate_i = '1' else userDataUpLink_i(95 downto 80);
- elink_640m_s(11) <= userDataUpLink_i(191 downto 176) when data_rate_i = '1' else (others => '0');
- elink_640m_s(12) <= userDataUpLink_i(207 downto 192) when data_rate_i = '1' else userDataUpLink_i(111 downto 96);
- elink_640m_s(13) <= userDataUpLink_i(223 downto 208) when data_rate_i = '1' else (others => '0');
-
- elink_320m_s(0) <= userDataUpLink_i(7 downto 0);
- elink_320m_s(1) <= userDataUpLink_i(15 downto 8) when data_rate_i = '1' else (others => '0');
- elink_320m_s(2) <= userDataUpLink_i(23 downto 16) when data_rate_i = '1' else userDataUpLink_i(15 downto 8);
- elink_320m_s(3) <= userDataUpLink_i(31 downto 24) when data_rate_i = '1' else (others => '0');
- elink_320m_s(4) <= userDataUpLink_i(39 downto 32) when data_rate_i = '1' else userDataUpLink_i(23 downto 16);
- elink_320m_s(5) <= userDataUpLink_i(47 downto 40) when data_rate_i = '1' else (others => '0');
- elink_320m_s(6) <= userDataUpLink_i(55 downto 48) when data_rate_i = '1' else userDataUpLink_i(31 downto 24);
- elink_320m_s(7) <= userDataUpLink_i(63 downto 56) when data_rate_i = '1' else (others => '0');
- elink_320m_s(8) <= userDataUpLink_i(71 downto 64) when data_rate_i = '1' else userDataUpLink_i(39 downto 32);
- elink_320m_s(9) <= userDataUpLink_i(79 downto 72) when data_rate_i = '1' else (others => '0');
- elink_320m_s(10) <= userDataUpLink_i(87 downto 80) when data_rate_i = '1' else userDataUpLink_i(47 downto 40);
- elink_320m_s(11) <= userDataUpLink_i(95 downto 88) when data_rate_i = '1' else (others => '0');
- elink_320m_s(12) <= userDataUpLink_i(103 downto 96) when data_rate_i = '1' else userDataUpLink_i(55 downto 48);
- elink_320m_s(13) <= userDataUpLink_i(111 downto 104) when data_rate_i = '1' else (others => '0');
- elink_320m_s(14) <= userDataUpLink_i(119 downto 112) when data_rate_i = '1' else userDataUpLink_i(63 downto 56);
- elink_320m_s(15) <= userDataUpLink_i(127 downto 120) when data_rate_i = '1' else (others => '0');
- elink_320m_s(16) <= userDataUpLink_i(135 downto 128) when data_rate_i = '1' else userDataUpLink_i(71 downto 64);
- elink_320m_s(17) <= userDataUpLink_i(143 downto 136) when data_rate_i = '1' else (others => '0');
- elink_320m_s(18) <= userDataUpLink_i(151 downto 144) when data_rate_i = '1' else userDataUpLink_i(79 downto 72);
- elink_320m_s(19) <= userDataUpLink_i(159 downto 152) when data_rate_i = '1' else (others => '0');
- elink_320m_s(20) <= userDataUpLink_i(167 downto 160) when data_rate_i = '1' else userDataUpLink_i(87 downto 80);
- elink_320m_s(21) <= userDataUpLink_i(175 downto 168) when data_rate_i = '1' else (others => '0');
- elink_320m_s(22) <= userDataUpLink_i(183 downto 176) when data_rate_i = '1' else userDataUpLink_i(95 downto 88);
- elink_320m_s(23) <= userDataUpLink_i(191 downto 184) when data_rate_i = '1' else (others => '0');
- elink_320m_s(24) <= userDataUpLink_i(199 downto 192) when data_rate_i = '1' else userDataUpLink_i(103 downto 96);
- elink_320m_s(25) <= userDataUpLink_i(207 downto 200) when data_rate_i = '1' else (others => '0');
- elink_320m_s(26) <= userDataUpLink_i(215 downto 208) when data_rate_i = '1' else userDataUpLink_i(111 downto 104);
- elink_320m_s(27) <= userDataUpLink_i(223 downto 216) when data_rate_i = '1' else (others => '0');
-
- elink_160m_s(0) <= userDataUpLink_i(3 downto 0);
- elink_160m_s(1) <= userDataUpLink_i(7 downto 4);
- elink_160m_s(2) <= userDataUpLink_i(11 downto 8);
- elink_160m_s(3) <= userDataUpLink_i(15 downto 12);
- elink_160m_s(4) <= userDataUpLink_i(19 downto 16);
- elink_160m_s(5) <= userDataUpLink_i(23 downto 20);
- elink_160m_s(6) <= userDataUpLink_i(27 downto 24);
- elink_160m_s(7) <= userDataUpLink_i(31 downto 28);
- elink_160m_s(8) <= userDataUpLink_i(35 downto 32);
- elink_160m_s(9) <= userDataUpLink_i(39 downto 36);
- elink_160m_s(10) <= userDataUpLink_i(43 downto 40);
- elink_160m_s(11) <= userDataUpLink_i(47 downto 44);
- elink_160m_s(12) <= userDataUpLink_i(51 downto 48);
- elink_160m_s(13) <= userDataUpLink_i(55 downto 52);
- elink_160m_s(14) <= userDataUpLink_i(59 downto 56);
- elink_160m_s(15) <= userDataUpLink_i(63 downto 60);
- elink_160m_s(16) <= userDataUpLink_i(67 downto 64);
- elink_160m_s(17) <= userDataUpLink_i(71 downto 68);
- elink_160m_s(18) <= userDataUpLink_i(75 downto 72);
- elink_160m_s(19) <= userDataUpLink_i(79 downto 76);
- elink_160m_s(20) <= userDataUpLink_i(83 downto 80);
- elink_160m_s(21) <= userDataUpLink_i(87 downto 84);
- elink_160m_s(22) <= userDataUpLink_i(91 downto 88);
- elink_160m_s(23) <= userDataUpLink_i(95 downto 92);
- elink_160m_s(24) <= userDataUpLink_i(99 downto 96);
- elink_160m_s(25) <= userDataUpLink_i(103 downto 100);
- elink_160m_s(26) <= userDataUpLink_i(107 downto 104);
- elink_160m_s(27) <= userDataUpLink_i(111 downto 108);
-
- multi_elink_1g28_gen: for i in 0 to 6 generate
+ elink_1g28_s(0) <= USErDataUpLink_i(31 downto 0);
+ elink_1g28_s(1) <= USErDataUpLink_i(63 downto 32);
+ elink_1g28_s(2) <= USErDataUpLink_i(95 downto 64);
+ elink_1g28_s(3) <= USErDataUpLink_i(127 downto 96);
+ elink_1g28_s(4) <= USErDataUpLink_i(159 downto 128);
+ elink_1g28_s(5) <= USErDataUpLink_i(191 downto 160);
+ elink_1g28_s(6) <= USErDataUpLink_i(223 downto 192);
+
+ elink_640m_s(0) <= USErDataUpLink_i(15 downto 0);
+ elink_640m_s(1) <= USErDataUpLink_i(31 downto 16) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_640m_s(2) <= USErDataUpLink_i(47 downto 32) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(31 downto 16);
+ elink_640m_s(3) <= USErDataUpLink_i(63 downto 48) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_640m_s(4) <= USErDataUpLink_i(79 downto 64) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(47 downto 32);
+ elink_640m_s(5) <= USErDataUpLink_i(95 downto 80) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_640m_s(6) <= USErDataUpLink_i(111 downto 96) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(63 downto 48);
+ elink_640m_s(7) <= USErDataUpLink_i(127 downto 112) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_640m_s(8) <= USErDataUpLink_i(143 downto 128) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(79 downto 64);
+ elink_640m_s(9) <= USErDataUpLink_i(159 downto 144) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_640m_s(10) <= USErDataUpLink_i(175 downto 160) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(95 downto 80);
+ elink_640m_s(11) <= USErDataUpLink_i(191 downto 176) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_640m_s(12) <= USErDataUpLink_i(207 downto 192) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(111 downto 96);
+ elink_640m_s(13) <= USErDataUpLink_i(223 downto 208) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+
+ elink_320m_s(0) <= USErDataUpLink_i(7 downto 0);
+ elink_320m_s(1) <= USErDataUpLink_i(15 downto 8) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(2) <= USErDataUpLink_i(23 downto 16) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(15 downto 8);
+ elink_320m_s(3) <= USErDataUpLink_i(31 downto 24) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(4) <= USErDataUpLink_i(39 downto 32) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(23 downto 16);
+ elink_320m_s(5) <= USErDataUpLink_i(47 downto 40) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(6) <= USErDataUpLink_i(55 downto 48) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(31 downto 24);
+ elink_320m_s(7) <= USErDataUpLink_i(63 downto 56) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(8) <= USErDataUpLink_i(71 downto 64) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(39 downto 32);
+ elink_320m_s(9) <= USErDataUpLink_i(79 downto 72) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(10) <= USErDataUpLink_i(87 downto 80) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(47 downto 40);
+ elink_320m_s(11) <= USErDataUpLink_i(95 downto 88) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(12) <= USErDataUpLink_i(103 downto 96) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(55 downto 48);
+ elink_320m_s(13) <= USErDataUpLink_i(111 downto 104) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(14) <= USErDataUpLink_i(119 downto 112) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(63 downto 56);
+ elink_320m_s(15) <= USErDataUpLink_i(127 downto 120) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(16) <= USErDataUpLink_i(135 downto 128) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(71 downto 64);
+ elink_320m_s(17) <= USErDataUpLink_i(143 downto 136) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(18) <= USErDataUpLink_i(151 downto 144) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(79 downto 72);
+ elink_320m_s(19) <= USErDataUpLink_i(159 downto 152) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(20) <= USErDataUpLink_i(167 downto 160) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(87 downto 80);
+ elink_320m_s(21) <= USErDataUpLink_i(175 downto 168) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(22) <= USErDataUpLink_i(183 downto 176) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(95 downto 88);
+ elink_320m_s(23) <= USErDataUpLink_i(191 downto 184) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(24) <= USErDataUpLink_i(199 downto 192) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(103 downto 96);
+ elink_320m_s(25) <= USErDataUpLink_i(207 downto 200) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+ elink_320m_s(26) <= USErDataUpLink_i(215 downto 208) WHEN data_rate_i = '1' ELSE USErDataUpLink_i(111 downto 104);
+ elink_320m_s(27) <= USErDataUpLink_i(223 downto 216) WHEN data_rate_i = '1' ELSE (OTHERS => '0');
+
+ elink_160m_s(0) <= USErDataUpLink_i(3 downto 0);
+ elink_160m_s(1) <= USErDataUpLink_i(7 downto 4);
+ elink_160m_s(2) <= USErDataUpLink_i(11 downto 8);
+ elink_160m_s(3) <= USErDataUpLink_i(15 downto 12);
+ elink_160m_s(4) <= USErDataUpLink_i(19 downto 16);
+ elink_160m_s(5) <= USErDataUpLink_i(23 downto 20);
+ elink_160m_s(6) <= USErDataUpLink_i(27 downto 24);
+ elink_160m_s(7) <= USErDataUpLink_i(31 downto 28);
+ elink_160m_s(8) <= USErDataUpLink_i(35 downto 32);
+ elink_160m_s(9) <= USErDataUpLink_i(39 downto 36);
+ elink_160m_s(10) <= USErDataUpLink_i(43 downto 40);
+ elink_160m_s(11) <= USErDataUpLink_i(47 downto 44);
+ elink_160m_s(12) <= USErDataUpLink_i(51 downto 48);
+ elink_160m_s(13) <= USErDataUpLink_i(55 downto 52);
+ elink_160m_s(14) <= USErDataUpLink_i(59 downto 56);
+ elink_160m_s(15) <= USErDataUpLink_i(63 downto 60);
+ elink_160m_s(16) <= USErDataUpLink_i(67 downto 64);
+ elink_160m_s(17) <= USErDataUpLink_i(71 downto 68);
+ elink_160m_s(18) <= USErDataUpLink_i(75 downto 72);
+ elink_160m_s(19) <= USErDataUpLink_i(79 downto 76);
+ elink_160m_s(20) <= USErDataUpLink_i(83 downto 80);
+ elink_160m_s(21) <= USErDataUpLink_i(87 downto 84);
+ elink_160m_s(22) <= USErDataUpLink_i(91 downto 88);
+ elink_160m_s(23) <= USErDataUpLink_i(95 downto 92);
+ elink_160m_s(24) <= USErDataUpLink_i(99 downto 96);
+ elink_160m_s(25) <= USErDataUpLink_i(103 downto 100);
+ elink_160m_s(26) <= USErDataUpLink_i(107 downto 104);
+ elink_160m_s(27) <= USErDataUpLink_i(111 downto 108);
+
+ multi_elink_1g28_gen: FOR i IN 0 TO 6 GENERATE
prbs7_32b_checker_inst: prbs7_32b_checker
- port map(
+ PORT MAP(
reset_i => reset320_s,
clk_i => ser320_clk_i,
clken_i => ser320_clkEn_i,
@@ -210,7 +210,7 @@ begin
err_o => elink_1g28_err_s(i*4),
rdy_o => elink_1g28_prbsRdy_s(i*4)
);
- end generate;
+ END GENERATE;
elink_1g28_prbsRdy_s(3 downto 1) <= "000";
elink_1g28_prbsRdy_s(7 downto 5) <= "000";
@@ -220,9 +220,9 @@ begin
elink_1g28_prbsRdy_s(23 downto 21) <= "000";
elink_1g28_prbsRdy_s(27 downto 25) <= "000";
- multi_elink_640mbps_gen: for i in 0 to 13 generate
+ multi_elink_640mbps_gen: FOR i IN 0 TO 13 GENERATE
prbs7_16b_checker_inst: prbs7_16b_checker
- port map(
+ PORT MAP(
reset_i => reset320_s,
clk_i => ser320_clk_i,
clken_i => ser320_clkEn_i,
@@ -230,7 +230,7 @@ begin
err_o => elink_640m_err_s(i*2),
rdy_o => elink_640m_prbsRdy_s(i*2)
);
- end generate;
+ END GENERATE;
elink_640m_prbsRdy_s(1) <= '0';
elink_640m_prbsRdy_s(3) <= '0';
@@ -247,9 +247,9 @@ begin
elink_640m_prbsRdy_s(25) <= '0';
elink_640m_prbsRdy_s(27) <= '0';
- multi_elink_320mbps_gen: for i in 0 to 27 generate
+ multi_elink_320mbps_gen: FOR i IN 0 TO 27 GENERATE
prbs7_8b_checker_inst: prbs7_8b_checker
- port map(
+ PORT MAP(
reset_i => reset320_s,
clk_i => ser320_clk_i,
clken_i => ser320_clkEn_i,
@@ -257,11 +257,11 @@ begin
err_o => elink_320m_err_s(i),
rdy_o => elink_320m_prbsRdy_s(i)
);
- end generate;
+ END GENERATE;
- multi_elink_160mbps_gen: for i in 0 to 27 generate
+ multi_elink_160mbps_gen: FOR i IN 0 TO 27 GENERATE
prbs7_4b_checker_inst: prbs7_4b_checker
- port map(
+ PORT MAP(
reset_i => reset320_s,
clk_i => ser320_clk_i,
clken_i => ser320_clkEn_i,
@@ -269,23 +269,23 @@ begin
err_o => elink_160m_err_s(i),
rdy_o => elink_160m_prbsRdy_s(i)
);
- end generate;
+ END GENERATE;
- err_cnter_gen: for i in 0 to 27 generate
+ err_cnter_gen: FOR i IN 0 TO 27 GENERATE
- elink_err_s(i) <= elink_1g28_err_s(i) when elink_config_i(i) = "11" else
- x"0000" & elink_640m_err_s(i) when elink_config_i(i) = "10" else
- x"000000" & elink_320m_err_s(i) when elink_config_i(i) = "01" else
+ elink_err_s(i) <= elink_1g28_err_s(i) WHEN elink_config_i(i) = "11" ELSE
+ x"0000" & elink_640m_err_s(i) WHEN elink_config_i(i) = "10" ELSE
+ x"000000" & elink_320m_err_s(i) WHEN elink_config_i(i) = "01" ELSE
x"0000000" & elink_160m_err_s(i);
- elink_prbs_rdy(i) <= elink_1g28_prbsRdy_s(i) when elink_config_i(i) = "11" else
- elink_640m_prbsRdy_s(i) when elink_config_i(i) = "10" else
- elink_320m_prbsRdy_s(i) when elink_config_i(i) = "01" else
+ elink_prbs_rdy(i) <= elink_1g28_prbsRdy_s(i) WHEN elink_config_i(i) = "11" ELSE
+ elink_640m_prbsRdy_s(i) WHEN elink_config_i(i) = "10" ELSE
+ elink_320m_prbsRdy_s(i) WHEN elink_config_i(i) = "01" ELSE
elink_160m_prbsRdy_s(i);
- error_detected_o(i) <= '0' when elink_err_s(i) = x"00000000" else '1';
+ error_detected_o(i) <= '0' WHEN elink_err_s(i) = x"00000000" ELSE '1';
- end generate;
+ END GENERATE;
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/lpgbtfpga_patterngen.vhd b/hdl/lpgbtfpga_patterngen.vhd
index 1eb9b11e3c8fda7d90e2935ca86f47bdbf37435b..e48df8579add6ac9bc318da1e9446e47bd5e5b29 100644
--- a/hdl/lpgbtfpga_patterngen.vhd
+++ b/hdl/lpgbtfpga_patterngen.vhd
@@ -1,12 +1,12 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.numeric_std.all;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.all;
-entity lpgbtfpga_patterngen is
- port(
+ENTITY lpgbtfpga_patterngen IS
+ PORT(
--clk40Mhz_Tx_i : in std_logic;
clk320DnLink_i : in std_logic;
- clkEnDnLink_i : in std_logic;
+ clkENDnLink_i : in std_logic;
generator_rst_i : in std_logic;
@@ -19,18 +19,18 @@ entity lpgbtfpga_patterngen is
downlink_o : out std_logic_vector(31 downto 0);
- eport_gen_rdy_o : out std_logic_vector(15 downto 0)
+ ePORT_gen_rdy_o : out std_logic_vector(15 downto 0)
);
-end lpgbtfpga_patterngen;
+END lpgbtfpga_patterngen;
-architecture rtl of lpgbtfpga_patterngen is
+ARCHITECTURE rtl OF lpgbtfpga_patterngen IS
-- EPORT generators
- component prbs7_2b_generator
- generic(
+ COMPONENT prbs7_2b_generator
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -39,13 +39,13 @@ architecture rtl of lpgbtfpga_patterngen is
prbs_word_o : out std_logic_vector(1 downto 0);
rdy_o : out std_logic
);
- end component;
+ END COMPONENT;
- component prbs7_4b_generator
- generic(
+ COMPONENT prbs7_4b_generator
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -54,13 +54,13 @@ architecture rtl of lpgbtfpga_patterngen is
prbs_word_o : out std_logic_vector(3 downto 0);
rdy_o : out std_logic
);
- end component;
+ END COMPONENT;
- component prbs7_8b_generator
- generic(
+ COMPONENT prbs7_8b_generator
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -69,97 +69,97 @@ architecture rtl of lpgbtfpga_patterngen is
prbs_word_o : out std_logic_vector(7 downto 0);
rdy_o : out std_logic
);
- end component;
+ END COMPONENT;
- type elink_80prbs_arr_T is array (integer range <>) of std_logic_vector(1 downto 0);
- type elink_160prbs_arr_T is array (integer range <>) of std_logic_vector(3 downto 0);
- type elink_320prbs_arr_T is array (integer range <>) of std_logic_vector(7 downto 0);
+ TYPE elink_80prbs_arr_T is array (integer range <>) of std_logic_vector(1 downto 0);
+ TYPE elink_160prbs_arr_T is array (integer range <>) of std_logic_vector(3 downto 0);
+ TYPE elink_320prbs_arr_T is array (integer range <>) of std_logic_vector(7 downto 0);
- signal reset_synch_s : std_logic;
- signal prbs7_80data_s : elink_80prbs_arr_T(15 downto 0);
- signal prbs7_160data_s : elink_160prbs_arr_T(7 downto 0);
- signal prbs7_320data_s : elink_320prbs_arr_T(3 downto 0);
- signal rst_dst_s : std_logic;
+ SIGNAL reset_synch_s : std_logic;
+ SIGNAL prbs7_80data_s : elink_80prbs_arr_T(15 downto 0);
+ SIGNAL prbs7_160data_s : elink_160prbs_arr_T(7 downto 0);
+ SIGNAL prbs7_320data_s : elink_320prbs_arr_T(3 downto 0);
+ SIGNAL rst_dst_s : std_logic;
-begin
+BEGIN
- reset_synch_proc: process(generator_rst_i, clk320DnLink_i)
- begin
- if generator_rst_i = '1' then
+ reset_synch_proc: PROCESS(generator_rst_i, clk320DnLink_i)
+ BEGIN
+ IF generator_rst_i = '1' THEN
rst_dst_s <= '1';
reset_synch_s <= '1';
- elsif rising_edge(clk320DnLink_i) then
+ ELSIF rising_edge(clk320DnLink_i) THEN
rst_dst_s <= '0';
reset_synch_s <= rst_dst_s;
- end if;
- end process;
+ END IF;
+ END PROCESS;
- multi_elink_gen_80mbps: for i in 0 to 15 generate
+ multi_elink_gen_80mbps: FOR i IN 0 TO 15 GENERATE
prbs7_2b_generator_inst: prbs7_2b_generator
- generic map(
+ GENERIC MAP(
INIT_c => x"a4"
)
- port map(
+ PORT MAP(
reset_i => reset_synch_s,
clk_i => clk320DnLink_i,
- clken_i => clkEnDnLink_i,
- err_pattern_i => (others => '0'), -- No error injection
- rep_delay_i => (others => '0'), -- No error injection
+ clken_i => clkENDnLink_i,
+ err_pattern_i => (OTHERS => '0'), -- No error injection
+ rep_delay_i => (OTHERS => '0'), -- No error injection
prbs_word_o => prbs7_80data_s(i),
- rdy_o => eport_gen_rdy_o(i)
+ rdy_o => ePORT_gen_rdy_o(i)
);
- end generate;
+ END GENERATE;
- multi_elink_gen_160mbps: for i in 0 to 7 generate
+ multi_elink_gen_160mbps: FOR i IN 0 TO 7 GENERATE
prbs7_2b_generator_inst: prbs7_4b_generator
- generic map(
+ GENERIC MAP(
INIT_c => x"a4"
)
- port map(
+ PORT MAP(
reset_i => reset_synch_s,
clk_i => clk320DnLink_i,
- clken_i => clkEnDnLink_i,
- err_pattern_i => (others => '0'), -- No error injection
- rep_delay_i => (others => '0'), -- No error injection
+ clken_i => clkENDnLink_i,
+ err_pattern_i => (OTHERS => '0'), -- No error injection
+ rep_delay_i => (OTHERS => '0'), -- No error injection
prbs_word_o => prbs7_160data_s(i),
- rdy_o => eport_gen_rdy_o(i)
+ rdy_o => ePORT_gen_rdy_o(i)
);
- end generate;
+ END GENERATE;
- multi_elink_gen_320mbps: for i in 0 to 3 generate
+ multi_elink_gen_320mbps: FOR i IN 0 TO 3 GENERATE
prbs7_2b_generator_inst: prbs7_8b_generator
- generic map(
+ GENERIC MAP(
INIT_c => x"a4"
)
- port map(
+ PORT MAP(
reset_i => reset_synch_s,
clk_i => clk320DnLink_i,
- clken_i => clkEnDnLink_i,
- err_pattern_i => (others => '0'), -- No error injection
- rep_delay_i => (others => '0'), -- No error injection
+ clken_i => clkENDnLink_i,
+ err_pattern_i => (OTHERS => '0'), -- No error injection
+ rep_delay_i => (OTHERS => '0'), -- No error injection
prbs_word_o => prbs7_320data_s(i),
- rdy_o => eport_gen_rdy_o(i)
+ rdy_o => ePORT_gen_rdy_o(i)
);
- end generate;
+ END GENERATE;
- downlink_o(7 downto 0) <= prbs7_320data_s(0) when config_group0_i = "11" else
- prbs7_160data_s(1) & prbs7_160data_s(0) when config_group0_i = "10" else
- prbs7_80data_s(3) & prbs7_80data_s(2) & prbs7_80data_s(1) & prbs7_80data_s(0) when config_group0_i = "01" else
+ downlink_o(7 downto 0) <= prbs7_320data_s(0) WHEN config_group0_i = "11" ELSE
+ prbs7_160data_s(1) & prbs7_160data_s(0) WHEN config_group0_i = "10" ELSE
+ prbs7_80data_s(3) & prbs7_80data_s(2) & prbs7_80data_s(1) & prbs7_80data_s(0) WHEN config_group0_i = "01" ELSE
fixed_pattern_i(7 downto 0);
- downlink_o(15 downto 8) <= prbs7_320data_s(1) when config_group1_i = "11" else
- prbs7_160data_s(3) & prbs7_160data_s(2) when config_group1_i = "10" else
- prbs7_80data_s(7) & prbs7_80data_s(6) & prbs7_80data_s(5) & prbs7_80data_s(4) when config_group0_i = "01" else
+ downlink_o(15 downto 8) <= prbs7_320data_s(1) WHEN config_group1_i = "11" ELSE
+ prbs7_160data_s(3) & prbs7_160data_s(2) WHEN config_group1_i = "10" ELSE
+ prbs7_80data_s(7) & prbs7_80data_s(6) & prbs7_80data_s(5) & prbs7_80data_s(4) WHEN config_group0_i = "01" ELSE
fixed_pattern_i(15 downto 8);
- downlink_o(23 downto 16) <= prbs7_320data_s(2) when config_group2_i = "11" else
- prbs7_160data_s(5) & prbs7_160data_s(4) when config_group2_i = "10" else
- prbs7_80data_s(11) & prbs7_80data_s(10) & prbs7_80data_s(9) & prbs7_80data_s(8) when config_group0_i = "01" else
+ downlink_o(23 downto 16) <= prbs7_320data_s(2) WHEN config_group2_i = "11" ELSE
+ prbs7_160data_s(5) & prbs7_160data_s(4) WHEN config_group2_i = "10" ELSE
+ prbs7_80data_s(11) & prbs7_80data_s(10) & prbs7_80data_s(9) & prbs7_80data_s(8) WHEN config_group0_i = "01" ELSE
fixed_pattern_i(23 downto 16);
- downlink_o(31 downto 24) <= prbs7_320data_s(3) when config_group3_i = "11" else
- prbs7_160data_s(7) & prbs7_160data_s(6) when config_group3_i = "10" else
- prbs7_80data_s(15) & prbs7_80data_s(14) & prbs7_80data_s(13) & prbs7_80data_s(12) when config_group0_i = "01" else
+ downlink_o(31 downto 24) <= prbs7_320data_s(3) WHEN config_group3_i = "11" ELSE
+ prbs7_160data_s(7) & prbs7_160data_s(6) WHEN config_group3_i = "10" ELSE
+ prbs7_80data_s(15) & prbs7_80data_s(14) & prbs7_80data_s(13) & prbs7_80data_s(12) WHEN config_group0_i = "01" ELSE
fixed_pattern_i(31 downto 24);
-end rtl;
+END rtl;
diff --git a/hdl/prbs/prbs7_16b_checker.vhd b/hdl/prbs/prbs7_16b_checker.vhd
index cc0fae79bf73a57a162160d3e0bee763bf844920..9aab90a2201289f09a33f77d783aeb2b4c78c374 100644
--- a/hdl/prbs/prbs7_16b_checker.vhd
+++ b/hdl/prbs/prbs7_16b_checker.vhd
@@ -1,10 +1,10 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_16b_checker is
- port (
+ENTITY prbs7_16b_checker IS
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -12,57 +12,57 @@ entity prbs7_16b_checker is
err_o : out std_logic_vector(15 downto 0);
rdy_o : out std_logic
);
-end prbs7_16b_checker;
+END prbs7_16b_checker;
-architecture rtl of prbs7_16b_checker is
- signal feedback_reg : std_logic_vector(15 downto 0);
- signal err_s : std_logic_vector(15 downto 0);
+ARCHITECTURE rtl OF prbs7_16b_checker IS
+ SIGNAL feedback_reg : std_logic_vector(15 downto 0);
+ SIGNAL err_s : std_logic_vector(15 downto 0);
- type checker_state_T is (waitForLock, Locked);
- signal status : checker_state_T;
+ TYPE checker_state_T is (waitFORLock, Locked);
+ SIGNAL status : checker_state_T;
- constant STATS_CONFIG_c : integer := 10;
- signal cnt_stats : integer range 0 to STATS_CONFIG_c;
+ CONSTANT STATS_CONFIG_c : integer := 10;
+ SIGNAL cnt_stats : integer range 0 to STATS_CONFIG_c;
-begin
+BEGIN
- checker_fsm_proc: process(reset_i, clk_i)
- begin
- if reset_i = '1' then
- status <= waitForLock;
+ checker_fsm_proc: PROCESS(reset_i, clk_i)
+ BEGIN
+ IF reset_i = '1' THEN
+ status <= waitFORLock;
cnt_stats <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
case status is
- when waitForLock =>
- if cnt_stats= STATS_CONFIG_c then
+ WHEN waitFORLock =>
+ IF cnt_stats= STATS_CONFIG_c THEN
status <= Locked;
- else
- if err_s = x"0000" and feedback_reg /= x"0000" then
+ ELSE
+ IF err_s = x"0000" and feedback_reg /= x"0000" THEN
cnt_stats <= cnt_stats + 1;
- else
+ ELSE
cnt_stats <= 0;
- end if;
- end if;
+ END IF;
+ END IF;
- when Locked => null;
- end case;
- end if;
- end process;
+ WHEN Locked => null;
+ END case;
+ END IF;
+ END PROCESS;
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- variable cnter : integer range 0 to 1;
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ VARIABLE cnter : integer range 0 to 1;
+ BEGIN
- if reset_i = '1' then
- feedback_reg <= (others => '0');
+ IF reset_i = '1' THEN
+ feedback_reg <= (OTHERS => '0');
err_s <= x"0000";
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
err_s(0) <= prbs_word_i(0) xor (feedback_reg(5) xor feedback_reg(4) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2));
err_s(1) <= prbs_word_i(1) xor (feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4) xor feedback_reg(5) xor feedback_reg(4) xor feedback_reg(4) xor feedback_reg(3));
@@ -81,9 +81,9 @@ begin
err_s(14) <= prbs_word_i(14) xor (feedback_reg(5) xor feedback_reg(4));
err_s(15) <= prbs_word_i(15) xor (feedback_reg(6) xor feedback_reg(5));
- if status /= Locked then
+ IF status /= Locked THEN
feedback_reg <= prbs_word_i;
- else
+ ELSE
feedback_reg(0) <= feedback_reg(5) xor feedback_reg(4) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2);
feedback_reg(1) <= feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4) xor feedback_reg(5) xor feedback_reg(4) xor feedback_reg(4) xor feedback_reg(3);
feedback_reg(2) <= feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4);
@@ -100,16 +100,16 @@ begin
feedback_reg(13) <= feedback_reg(4) xor feedback_reg(3);
feedback_reg(14) <= feedback_reg(5) xor feedback_reg(4);
feedback_reg(15) <= feedback_reg(6) xor feedback_reg(5);
- end if;
+ END IF;
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
err_o <= err_s;
- rdy_o <= '1' when status = Locked else '0';
+ rdy_o <= '1' WHEN status = Locked ELSE '0';
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_1b_checker.vhd b/hdl/prbs/prbs7_1b_checker.vhd
index 77d45053c59acc36af84c7643bf237fb874e9803..7604236749047013f0b9a35df99f4962a6f14c31 100644
--- a/hdl/prbs/prbs7_1b_checker.vhd
+++ b/hdl/prbs/prbs7_1b_checker.vhd
@@ -1,10 +1,10 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_1b_checker is
- port (
+ENTITY prbs7_1b_checker IS
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -12,68 +12,68 @@ entity prbs7_1b_checker is
err_o : out std_logic_vector(3 downto 0);
rdy_o : out std_logic
);
-end prbs7_1b_checker;
+END prbs7_1b_checker;
-architecture rtl of prbs7_1b_checker is
- signal feedback_reg : std_logic_vector(7 downto 0);
- signal err_s : std_logic_vector(3 downto 0);
+ARCHITECTURE rtl OF prbs7_1b_checker IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0);
+ SIGNAL err_s : std_logic_vector(3 downto 0);
- type checker_state_T is (waitForLock, Locked);
- signal status : checker_state_T;
+ TYPE checker_state_T is (waitFORLock, Locked);
+ SIGNAL status : checker_state_T;
- constant STATS_CONFIG_c : integer := 10;
- signal cnt_stats : integer range 0 to STATS_CONFIG_c;
-begin
+ CONSTANT STATS_CONFIG_c : integer := 10;
+ SIGNAL cnt_stats : integer range 0 to STATS_CONFIG_c;
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- checker_fsm_proc: process(reset_i, clk_i)
- begin
- if reset_i = '1' then
- status <= waitForLock;
+ checker_fsm_proc: PROCESS(reset_i, clk_i)
+ BEGIN
+ IF reset_i = '1' THEN
+ status <= waitFORLock;
cnt_stats <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
case status is
- when waitForLock =>
- if err_s = "0000" and feedback_reg /= x"00" then
+ WHEN waitFORLock =>
+ IF err_s = "0000" and feedback_reg /= x"00" THEN
cnt_stats <= cnt_stats + 1;
- else
+ ELSE
cnt_stats <= 0;
- end if;
+ END IF;
- if cnt_stats= STATS_CONFIG_c then
+ IF cnt_stats= STATS_CONFIG_c THEN
status <= Locked;
- end if;
+ END IF;
- when Locked => null;
- end case;
- end if;
- end process;
+ WHEN Locked => null;
+ END case;
+ END IF;
+ END PROCESS;
- prbs7_proc: process(reset_i, clk_i)
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ BEGIN
- if reset_i = '1' then
- feedback_reg <= (others => '0');
+ IF reset_i = '1' THEN
+ feedback_reg <= (OTHERS => '0');
err_s <= "0000";
- elsif rising_edge(clk_i) then
- if clken_i = '1' then
+ ELSIF rising_edge(clk_i) THEN
+ IF clken_i = '1' THEN
err_s(0) <= (feedback_reg(6) xor feedback_reg(5)) xor prbs_word_i;
err_s(3 downto 1) <= "000";
feedback_reg(7 downto 1) <= feedback_reg(6 downto 0);
- if status /= Locked then
+ IF status /= Locked THEN
feedback_reg(0) <= prbs_word_i;
- else
+ ELSE
feedback_reg(0) <= (feedback_reg(5) xor feedback_reg(6));
- end if;
- end if;
- end if;
- end process;
+ END IF;
+ END IF;
+ END IF;
+ END PROCESS;
err_o <= err_s;
- rdy_o <= '1' when status = Locked else '0';
+ rdy_o <= '1' WHEN status = Locked ELSE '0';
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_1b_generator.vhd b/hdl/prbs/prbs7_1b_generator.vhd
index 15b54cae1bcc5f55d01e135ec8b98863b6b28341..b31405d7516e54d730c93ec24748fedb7dab5fcd 100644
--- a/hdl/prbs/prbs7_1b_generator.vhd
+++ b/hdl/prbs/prbs7_1b_generator.vhd
@@ -1,13 +1,13 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_1b_generator is
- generic(
+ENTITY prbs7_1b_generator IS
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -16,71 +16,71 @@ entity prbs7_1b_generator is
prbs_word_o : out std_logic;
rdy_o : out std_logic
);
-end prbs7_1b_generator;
+END prbs7_1b_generator;
-architecture rtl of prbs7_1b_generator is
- signal feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
- signal prbs_word_s : std_logic;
- signal err_cnter_s : unsigned(24 downto 0);
- signal inject_error_s : std_logic;
- signal onceinject_done_s : std_logic;
- signal err_patt_pos_s : integer range 0 to 7;
- signal err_pattern_s : std_logic;
+ARCHITECTURE rtl OF prbs7_1b_generator IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
+ SIGNAL prbs_word_s : std_logic;
+ SIGNAL err_cnter_s : unsigned(24 downto 0);
+ SIGNAL inject_error_s : std_logic;
+ SIGNAL onceinject_done_s : std_logic;
+ SIGNAL err_patt_pos_s : integer range 0 to 7;
+ SIGNAL err_pattern_s : std_logic;
-begin
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ BEGIN
- if reset_i = '1' then
+ IF reset_i = '1' THEN
feedback_reg <= INIT_c;
prbs_word_s <= '0';
rdy_o <= '0';
- err_cnter_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
err_pattern_s <= '0';
err_patt_pos_s <= 0;
- elsif rising_edge(clk_i) then
- if clken_i = '1' then
+ ELSIF rising_edge(clk_i) THEN
+ IF clken_i = '1' THEN
rdy_o <= '1';
prbs_word_s <= feedback_reg(6) xor feedback_reg(5);
feedback_reg <= feedback_reg(6 downto 0) & (feedback_reg(6) xor feedback_reg(5));
err_pattern_s <= '0';
- if err_pattern_i /= x"00" then
- if std_logic_vector(err_cnter_s) = rep_delay_i then
- if rep_delay_i /= x"000000" or onceinject_done_s = '0' then
+ IF err_pattern_i /= x"00" THEN
+ IF std_logic_vector(err_cnter_s) = rep_delay_i THEN
+ IF rep_delay_i /= x"000000" or onceinject_done_s = '0' THEN
err_pattern_s <= err_pattern_i(err_patt_pos_s);
- if err_patt_pos_s = 7 then
+ IF err_patt_pos_s = 7 THEN
err_patt_pos_s <= 0;
- err_cnter_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '1';
- else
+ ELSE
err_patt_pos_s <= err_patt_pos_s+1;
- end if;
- end if;
- else
- if err_patt_pos_s = 7 then
+ END IF;
+ END IF;
+ ELSE
+ IF err_patt_pos_s = 7 THEN
err_cnter_s <= err_cnter_s + 1;
err_patt_pos_s <= 0;
- else
+ ELSE
err_patt_pos_s <= err_patt_pos_s + 1;
- end if;
- end if;
- else
- err_cnter_s <= (others => '0');
+ END IF;
+ END IF;
+ ELSE
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '0';
err_patt_pos_s <= 0;
- end if;
- end if;
- end if;
+ END IF;
+ END IF;
+ END IF;
- end process;
+ END PROCESS;
prbs_word_o <= prbs_word_s xor err_pattern_s;
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_2b_checker.vhd b/hdl/prbs/prbs7_2b_checker.vhd
index 90fee2c5db866f99de3e60901669eb37442a61cf..58b0c471f36f869dab1642f721439f05668c87f0 100644
--- a/hdl/prbs/prbs7_2b_checker.vhd
+++ b/hdl/prbs/prbs7_2b_checker.vhd
@@ -1,10 +1,10 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_2b_checker is
- port (
+ENTITY prbs7_2b_checker IS
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
@@ -13,56 +13,56 @@ entity prbs7_2b_checker is
err_o : out std_logic_vector(3 downto 0);
rdy_o : out std_logic
);
-end prbs7_2b_checker;
+END prbs7_2b_checker;
-architecture rtl of prbs7_2b_checker is
- signal feedback_reg : std_logic_vector(7 downto 0);
- signal err_s : std_logic_vector(3 downto 0);
+ARCHITECTURE rtl OF prbs7_2b_checker IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0);
+ SIGNAL err_s : std_logic_vector(3 downto 0);
- type checker_state_T is (waitForLock, Locked);
- signal status : checker_state_T;
+ TYPE checker_state_T is (waitFORLock, Locked);
+ SIGNAL status : checker_state_T;
- constant STATS_CONFIG_c : integer := 10;
- signal cnt_stats : integer range 0 to STATS_CONFIG_c;
-begin
+ CONSTANT STATS_CONFIG_c : integer := 10;
+ SIGNAL cnt_stats : integer range 0 to STATS_CONFIG_c;
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- checker_fsm_proc: process(reset_i, clk_i)
- begin
- if reset_i = '1' then
- status <= waitForLock;
+ checker_fsm_proc: PROCESS(reset_i, clk_i)
+ BEGIN
+ IF reset_i = '1' THEN
+ status <= waitFORLock;
cnt_stats <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
case status is
- when waitForLock =>
+ WHEN waitFORLock =>
- if cnt_stats= STATS_CONFIG_c then
+ IF cnt_stats= STATS_CONFIG_c THEN
status <= Locked;
- else
- if err_s = "0000" and feedback_reg /= x"00" then
+ ELSE
+ IF err_s = "0000" and feedback_reg /= x"00" THEN
cnt_stats <= cnt_stats + 1;
- else
+ ELSE
cnt_stats <= 0;
- end if;
- end if;
+ END IF;
+ END IF;
- when Locked => null;
- end case;
- end if;
- end process;
+ WHEN Locked => null;
+ END case;
+ END IF;
+ END PROCESS;
- prbs7_proc: process(reset_i, clk_i)
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ BEGIN
- if reset_i = '1' then
- feedback_reg <= (others => '0');
+ IF reset_i = '1' THEN
+ feedback_reg <= (OTHERS => '0');
err_s <= "0000";
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
err_s(0) <= (feedback_reg(4) xor feedback_reg(5)) xor prbs_word_i(0);
err_s(1) <= (feedback_reg(6) xor feedback_reg(5)) xor prbs_word_i(1);
@@ -71,20 +71,20 @@ begin
feedback_reg(7 downto 2) <= feedback_reg(5 downto 0);
- if status /= Locked then
+ IF status /= Locked THEN
feedback_reg(0) <= prbs_word_i(0);
feedback_reg(1) <= prbs_word_i(1);
- else
+ ELSE
feedback_reg(0) <= (feedback_reg(4) xor feedback_reg(5));
feedback_reg(1) <= (feedback_reg(6) xor feedback_reg(5));
- end if;
- end if;
+ END IF;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
err_o <= err_s;
- rdy_o <= '1' when status = Locked else '0';
+ rdy_o <= '1' WHEN status = Locked ELSE '0';
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_2b_generator.vhd b/hdl/prbs/prbs7_2b_generator.vhd
index d38ab5b8d2596a719a47a96e2a00b15107d5d4c9..fcfe0a85421974286cec36198c18b3441350f353 100644
--- a/hdl/prbs/prbs7_2b_generator.vhd
+++ b/hdl/prbs/prbs7_2b_generator.vhd
@@ -1,13 +1,13 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_2b_generator is
- generic(
+ENTITY prbs7_2b_generator IS
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
@@ -18,37 +18,37 @@ entity prbs7_2b_generator is
prbs_word_o : out std_logic_vector(1 downto 0);
rdy_o : out std_logic
);
-end prbs7_2b_generator;
+END prbs7_2b_generator;
-architecture rtl of prbs7_2b_generator is
- signal feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
- signal prbs_word_s : std_logic_vector(1 downto 0);
- signal err_cnter_s : unsigned(24 downto 0);
- signal inject_error_s : std_logic;
- signal onceinject_done_s : std_logic;
- signal err_patt_pos_s : integer range 0 to 6;
- signal err_pattern_s : std_logic_vector(1 downto 0);
+ARCHITECTURE rtl OF prbs7_2b_generator IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
+ SIGNAL prbs_word_s : std_logic_vector(1 downto 0);
+ SIGNAL err_cnter_s : unsigned(24 downto 0);
+ SIGNAL inject_error_s : std_logic;
+ SIGNAL onceinject_done_s : std_logic;
+ SIGNAL err_patt_pos_s : integer range 0 to 6;
+ SIGNAL err_pattern_s : std_logic_vector(1 downto 0);
-begin
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- variable cnter : integer range 0 to 1;
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ VARIABLE cnter : integer range 0 to 1;
+ BEGIN
- if reset_i = '1' then
+ IF reset_i = '1' THEN
feedback_reg <= INIT_c;
- prbs_word_s <= (others => '0');
+ prbs_word_s <= (OTHERS => '0');
rdy_o <= '0';
- err_cnter_s <= (others => '0');
- err_pattern_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
+ err_pattern_s <= (OTHERS => '0');
err_patt_pos_s <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
rdy_o <= '1';
prbs_word_s(0) <= feedback_reg(5) xor feedback_reg(4);
@@ -60,44 +60,44 @@ begin
err_pattern_s <= "00";
- if err_pattern_i /= x"00" then
- if std_logic_vector(err_cnter_s) = rep_delay_i then
- if rep_delay_i /= x"000000" or onceinject_done_s = '0' then
+ IF err_pattern_i /= x"00" THEN
+ IF std_logic_vector(err_cnter_s) = rep_delay_i THEN
+ IF rep_delay_i /= x"000000" or onceinject_done_s = '0' THEN
err_pattern_s <= err_pattern_i(err_patt_pos_s+1 downto err_patt_pos_s);
- if err_patt_pos_s = 6 then
+ IF err_patt_pos_s = 6 THEN
err_patt_pos_s <= 0;
- err_cnter_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '1';
- elsif err_patt_pos_s = 2 then
+ ELSIF err_patt_pos_s = 2 THEN
err_patt_pos_s <= 4;
- elsif err_patt_pos_s = 4 then
+ ELSIF err_patt_pos_s = 4 THEN
err_patt_pos_s <= 6;
- else
+ ELSE
err_patt_pos_s <= 2;
- end if;
- end if;
- else
- if err_patt_pos_s = 6 then
+ END IF;
+ END IF;
+ ELSE
+ IF err_patt_pos_s = 6 THEN
err_cnter_s <= err_cnter_s + 1;
err_patt_pos_s <= 0;
- else
+ ELSE
err_patt_pos_s <= err_patt_pos_s + 2;
- end if;
- end if;
- else
- err_cnter_s <= (others => '0');
+ END IF;
+ END IF;
+ ELSE
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '0';
err_patt_pos_s <= 0;
- end if;
- end if;
+ END IF;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
prbs_word_o <= prbs_word_s xor err_pattern_s;
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_32b_checker.vhd b/hdl/prbs/prbs7_32b_checker.vhd
index 040a0ec1ce4ad7222075140a930c05563c8a50ea..a13b1a0a894ad41b63b2081abd1bee73a63fc886 100644
--- a/hdl/prbs/prbs7_32b_checker.vhd
+++ b/hdl/prbs/prbs7_32b_checker.vhd
@@ -1,10 +1,10 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_32b_checker is
- port (
+ENTITY prbs7_32b_checker IS
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -12,57 +12,57 @@ entity prbs7_32b_checker is
err_o : out std_logic_vector(31 downto 0);
rdy_o : out std_logic
);
-end prbs7_32b_checker;
+END prbs7_32b_checker;
-architecture rtl of prbs7_32b_checker is
- signal feedback_reg : std_logic_vector(31 downto 0);
- signal err_s : std_logic_vector(31 downto 0);
+ARCHITECTURE rtl OF prbs7_32b_checker IS
+ SIGNAL feedback_reg : std_logic_vector(31 downto 0);
+ SIGNAL err_s : std_logic_vector(31 downto 0);
- type checker_state_T is (waitForLock, Locked);
- signal status : checker_state_T;
+ TYPE checker_state_T is (waitFORLock, Locked);
+ SIGNAL status : checker_state_T;
- constant STATS_CONFIG_c : integer := 10;
- signal cnt_stats : integer range 0 to STATS_CONFIG_c;
+ CONSTANT STATS_CONFIG_c : integer := 10;
+ SIGNAL cnt_stats : integer range 0 to STATS_CONFIG_c;
-begin
+BEGIN
- checker_fsm_proc: process(reset_i, clk_i)
- begin
- if reset_i = '1' then
- status <= waitForLock;
+ checker_fsm_proc: PROCESS(reset_i, clk_i)
+ BEGIN
+ IF reset_i = '1' THEN
+ status <= waitFORLock;
cnt_stats <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
case status is
- when waitForLock =>
- if cnt_stats= STATS_CONFIG_c then
+ WHEN waitFORLock =>
+ IF cnt_stats= STATS_CONFIG_c THEN
status <= Locked;
- else
- if err_s = x"00000000" and feedback_reg /= x"00000000" then
+ ELSE
+ IF err_s = x"00000000" and feedback_reg /= x"00000000" THEN
cnt_stats <= cnt_stats + 1;
- else
+ ELSE
cnt_stats <= 0;
- end if;
- end if;
+ END IF;
+ END IF;
- when Locked => null;
- end case;
- end if;
- end process;
+ WHEN Locked => null;
+ END case;
+ END IF;
+ END PROCESS;
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- variable cnter : integer range 0 to 1;
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ VARIABLE cnter : integer range 0 to 1;
+ BEGIN
- if reset_i = '1' then
- feedback_reg <= (others => '0');
+ IF reset_i = '1' THEN
+ feedback_reg <= (OTHERS => '0');
err_s <= x"00000000";
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
err_s(0) <= prbs_word_i(0) xor (feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4));
err_s(1) <= prbs_word_i(1) xor (feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5));
@@ -97,9 +97,9 @@ begin
err_s(30) <= prbs_word_i(30) xor (feedback_reg(5) xor feedback_reg(4));
err_s(31) <= prbs_word_i(31) xor (feedback_reg(6) xor feedback_reg(5));
- if status /= Locked then
+ IF status /= Locked THEN
feedback_reg <= prbs_word_i;
- else
+ ELSE
feedback_reg(0) <= (feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4));
feedback_reg(1) <= (feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(1) xor feedback_reg(0) xor feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5));
feedback_reg(2) <= (feedback_reg(5) xor feedback_reg(4) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(4) xor feedback_reg(3) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(3) xor feedback_reg(2) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(2) xor feedback_reg(1) xor feedback_reg(1) xor feedback_reg(0));
@@ -132,16 +132,16 @@ begin
feedback_reg(29) <= (feedback_reg(4) xor feedback_reg(3));
feedback_reg(30) <= (feedback_reg(5) xor feedback_reg(4));
feedback_reg(31) <= (feedback_reg(6) xor feedback_reg(5));
- end if;
+ END IF;
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
err_o <= err_s;
- rdy_o <= '1' when status = Locked else '0';
+ rdy_o <= '1' WHEN status = Locked ELSE '0';
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_4b_checker.vhd b/hdl/prbs/prbs7_4b_checker.vhd
index 5bccc3fd3d2992a6eac061e651be47246bca0bff..93a166dabc3e0cb0209286daa61adcf62db58dbe 100644
--- a/hdl/prbs/prbs7_4b_checker.vhd
+++ b/hdl/prbs/prbs7_4b_checker.vhd
@@ -1,10 +1,10 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_4b_checker is
- port (
+ENTITY prbs7_4b_checker IS
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -12,56 +12,56 @@ entity prbs7_4b_checker is
err_o : out std_logic_vector(3 downto 0);
rdy_o : out std_logic
);
-end prbs7_4b_checker;
+END prbs7_4b_checker;
-architecture rtl of prbs7_4b_checker is
- signal feedback_reg : std_logic_vector(7 downto 0);
- signal err_s : std_logic_vector(3 downto 0);
+ARCHITECTURE rtl OF prbs7_4b_checker IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0);
+ SIGNAL err_s : std_logic_vector(3 downto 0);
- type checker_state_T is (waitForLock, Locked);
- signal status : checker_state_T;
+ TYPE checker_state_T is (waitFORLock, Locked);
+ SIGNAL status : checker_state_T;
- constant STATS_CONFIG_c : integer := 10;
- signal cnt_stats : integer range 0 to STATS_CONFIG_c;
-begin
+ CONSTANT STATS_CONFIG_c : integer := 10;
+ SIGNAL cnt_stats : integer range 0 to STATS_CONFIG_c;
+BEGIN
- checker_fsm_proc: process(reset_i, clk_i)
- begin
- if reset_i = '1' then
- status <= waitForLock;
+ checker_fsm_proc: PROCESS(reset_i, clk_i)
+ BEGIN
+ IF reset_i = '1' THEN
+ status <= waitFORLock;
cnt_stats <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
case status is
- when waitForLock =>
- if cnt_stats= STATS_CONFIG_c then
+ WHEN waitFORLock =>
+ IF cnt_stats= STATS_CONFIG_c THEN
status <= Locked;
- else
- if err_s = "0000" and feedback_reg /= x"00" then
+ ELSE
+ IF err_s = "0000" and feedback_reg /= x"00" THEN
cnt_stats <= cnt_stats + 1;
- else
+ ELSE
cnt_stats <= 0;
- end if;
- end if;
+ END IF;
+ END IF;
- when Locked => null;
- end case;
- end if;
- end process;
+ WHEN Locked => null;
+ END case;
+ END IF;
+ END PROCESS;
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- variable cnter : integer range 0 to 1;
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ VARIABLE cnter : integer range 0 to 1;
+ BEGIN
- if reset_i = '1' then
- feedback_reg <= (others => '0');
+ IF reset_i = '1' THEN
+ feedback_reg <= (OTHERS => '0');
err_s <= "0000";
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
err_s(0) <= (feedback_reg(2) xor feedback_reg(3)) xor prbs_word_i(0);
err_s(1) <= (feedback_reg(3) xor feedback_reg(4)) xor prbs_word_i(1);
@@ -69,26 +69,26 @@ begin
err_s(3) <= (feedback_reg(5) xor feedback_reg(6)) xor prbs_word_i(3);
feedback_reg(7 downto 4) <= feedback_reg(3 downto 0);
- if status /= Locked then
+ IF status /= Locked THEN
feedback_reg(0) <= prbs_word_i(0);
feedback_reg(1) <= prbs_word_i(1);
feedback_reg(2) <= prbs_word_i(2);
feedback_reg(3) <= prbs_word_i(3);
- else
+ ELSE
feedback_reg(0) <= (feedback_reg(2) xor feedback_reg(3));
feedback_reg(1) <= (feedback_reg(3) xor feedback_reg(4));
feedback_reg(2) <= (feedback_reg(4) xor feedback_reg(5));
feedback_reg(3) <= (feedback_reg(5) xor feedback_reg(6));
- end if;
+ END IF;
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
err_o <= err_s;
- rdy_o <= '1' when status = Locked else '0';
+ rdy_o <= '1' WHEN status = Locked ELSE '0';
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_4b_generator.vhd b/hdl/prbs/prbs7_4b_generator.vhd
index 740265f5e0b5736937dae23cac37ad207179d266..653e74f980503953d54c8e5ec3ca3705c0517d6b 100644
--- a/hdl/prbs/prbs7_4b_generator.vhd
+++ b/hdl/prbs/prbs7_4b_generator.vhd
@@ -1,13 +1,13 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_4b_generator is
- generic(
+ENTITY prbs7_4b_generator IS
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -18,36 +18,36 @@ entity prbs7_4b_generator is
prbs_word_o : out std_logic_vector(3 downto 0);
rdy_o : out std_logic
);
-end prbs7_4b_generator;
+END prbs7_4b_generator;
-architecture rtl of prbs7_4b_generator is
- signal feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
- signal prbs_word_s : std_logic_vector(3 downto 0);
- signal err_pattern_s : std_logic_vector(3 downto 0);
- signal err_cnter_s : unsigned(24 downto 0);
- signal inject_error_s : std_logic;
- signal onceinject_done_s : std_logic;
- signal err_patt_pos_s : integer range 0 to 4;
-begin
+ARCHITECTURE rtl OF prbs7_4b_generator IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
+ SIGNAL prbs_word_s : std_logic_vector(3 downto 0);
+ SIGNAL err_pattern_s : std_logic_vector(3 downto 0);
+ SIGNAL err_cnter_s : unsigned(24 downto 0);
+ SIGNAL inject_error_s : std_logic;
+ SIGNAL onceinject_done_s : std_logic;
+ SIGNAL err_patt_pos_s : integer range 0 to 4;
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- variable cnter : integer range 0 to 1;
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ VARIABLE cnter : integer range 0 to 1;
+ BEGIN
- if reset_i = '1' then
+ IF reset_i = '1' THEN
feedback_reg <= INIT_c;
- prbs_word_s <= (others => '0');
+ prbs_word_s <= (OTHERS => '0');
rdy_o <= '0';
- err_cnter_s <= (others => '0');
- err_pattern_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
+ err_pattern_s <= (OTHERS => '0');
err_patt_pos_s <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
rdy_o <= '1';
prbs_word_s(0) <= feedback_reg(2) xor feedback_reg(3);
@@ -63,38 +63,38 @@ begin
err_pattern_s <= x"0";
- if err_pattern_i /= x"00" then
- if std_logic_vector(err_cnter_s) = rep_delay_i then
- if rep_delay_i /= x"000000" or onceinject_done_s = '0' then
+ IF err_pattern_i /= x"00" THEN
+ IF std_logic_vector(err_cnter_s) = rep_delay_i THEN
+ IF rep_delay_i /= x"000000" or onceinject_done_s = '0' THEN
err_pattern_s <= err_pattern_i(err_patt_pos_s+3 downto err_patt_pos_s);
- if err_patt_pos_s = 4 then
+ IF err_patt_pos_s = 4 THEN
err_patt_pos_s <= 0;
- err_cnter_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '1';
- else
+ ELSE
err_patt_pos_s <= 4;
- end if;
- end if;
- else
- if err_patt_pos_s = 4 then
+ END IF;
+ END IF;
+ ELSE
+ IF err_patt_pos_s = 4 THEN
err_cnter_s <= err_cnter_s + 1;
err_patt_pos_s <= 0;
- else
+ ELSE
err_patt_pos_s <= 4;
- end if;
- end if;
- else
- err_cnter_s <= (others => '0');
+ END IF;
+ END IF;
+ ELSE
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '0';
err_patt_pos_s <= 0;
- end if;
+ END IF;
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
prbs_word_o <= prbs_word_s xor err_pattern_s;
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_64b_generator.vhd b/hdl/prbs/prbs7_64b_generator.vhd
index a72ee5def7d1482a6178ec6d3326c57ddd19459c..98b0c50d7d0b3e5f00c50d14bf317f41c52414e0 100644
--- a/hdl/prbs/prbs7_64b_generator.vhd
+++ b/hdl/prbs/prbs7_64b_generator.vhd
@@ -1,13 +1,13 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_64b_generator is
- generic(
+ENTITY prbs7_64b_generator IS
+ GENERIC(
INIT_c : in std_logic_vector(63 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clk_enable_i : in std_logic;
@@ -15,28 +15,28 @@ entity prbs7_64b_generator is
prbs_word_o : out std_logic_vector(63 downto 0);
rdy_o : out std_logic
);
-end prbs7_64b_generator;
+END prbs7_64b_generator;
-architecture rtl of prbs7_64b_generator is
- signal feedback_reg : std_logic_vector(63 downto 0) := INIT_c;
- signal prbs_word_s : std_logic_vector(63 downto 0) := INIT_c;
+ARCHITECTURE rtl OF prbs7_64b_generator IS
+ SIGNAL feedback_reg : std_logic_vector(63 downto 0) := INIT_c;
+ SIGNAL prbs_word_s : std_logic_vector(63 downto 0) := INIT_c;
-begin
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ BEGIN
- if reset_i = '1' then
+ IF reset_i = '1' THEN
feedback_reg <= INIT_c;
prbs_word_s <= INIT_c;
rdy_o <= '0';
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clk_enable_i = '1' then
+ IF clk_enable_i = '1' THEN
prbs_word_s <= feedback_reg;
rdy_o <= '1';
@@ -106,12 +106,12 @@ begin
feedback_reg(62) <= feedback_reg(5) xor feedback_reg(4);
feedback_reg(63) <= feedback_reg(6) xor feedback_reg(5);
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
prbs_word_o <= prbs_word_s;
-end rtl;
+END rtl;
diff --git a/hdl/prbs/prbs7_8b_checker.vhd b/hdl/prbs/prbs7_8b_checker.vhd
index 57f45ddfb4968b7875a2e0e6218a03abab82253b..614f2a2c0563ddeea7a6c4e5e56a8a6be1624b08 100644
--- a/hdl/prbs/prbs7_8b_checker.vhd
+++ b/hdl/prbs/prbs7_8b_checker.vhd
@@ -1,10 +1,10 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_8b_checker is
- port (
+ENTITY prbs7_8b_checker IS
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -12,57 +12,57 @@ entity prbs7_8b_checker is
err_o : out std_logic_vector(7 downto 0);
rdy_o : out std_logic
);
-end prbs7_8b_checker;
+END prbs7_8b_checker;
-architecture rtl of prbs7_8b_checker is
- signal feedback_reg : std_logic_vector(7 downto 0);
- signal err_s : std_logic_vector(7 downto 0);
+ARCHITECTURE rtl OF prbs7_8b_checker IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0);
+ SIGNAL err_s : std_logic_vector(7 downto 0);
- type checker_state_T is (waitForLock, Locked);
- signal status : checker_state_T;
+ TYPE checker_state_T is (waitFORLock, Locked);
+ SIGNAL status : checker_state_T;
- constant STATS_CONFIG_c : integer := 10;
- signal cnt_stats : integer range 0 to STATS_CONFIG_c;
+ CONSTANT STATS_CONFIG_c : integer := 10;
+ SIGNAL cnt_stats : integer range 0 to STATS_CONFIG_c;
-begin
+BEGIN
- checker_fsm_proc: process(reset_i, clk_i)
- begin
- if reset_i = '1' then
- status <= waitForLock;
+ checker_fsm_proc: PROCESS(reset_i, clk_i)
+ BEGIN
+ IF reset_i = '1' THEN
+ status <= waitFORLock;
cnt_stats <= 0;
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
case status is
- when waitForLock =>
- if cnt_stats= STATS_CONFIG_c then
+ WHEN waitFORLock =>
+ IF cnt_stats= STATS_CONFIG_c THEN
status <= Locked;
- else
- if err_s = x"00" and feedback_reg /= x"00" then
+ ELSE
+ IF err_s = x"00" and feedback_reg /= x"00" THEN
cnt_stats <= cnt_stats + 1;
- else
+ ELSE
cnt_stats <= 0;
- end if;
- end if;
+ END IF;
+ END IF;
- when Locked => null;
- end case;
- end if;
- end process;
+ WHEN Locked => null;
+ END case;
+ END IF;
+ END PROCESS;
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- variable cnter : integer range 0 to 1;
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ VARIABLE cnter : integer range 0 to 1;
+ BEGIN
- if reset_i = '1' then
- feedback_reg <= (others => '0');
+ IF reset_i = '1' THEN
+ feedback_reg <= (OTHERS => '0');
err_s <= x"00";
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
err_s(0) <= prbs_word_i(0) xor (feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4));
err_s(1) <= prbs_word_i(1) xor (feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5));
@@ -73,9 +73,9 @@ begin
err_s(6) <= prbs_word_i(6) xor (feedback_reg(5) xor feedback_reg(4));
err_s(7) <= prbs_word_i(7) xor (feedback_reg(6) xor feedback_reg(5));
- if status /= Locked then
+ IF status /= Locked THEN
feedback_reg <= prbs_word_i;
- else
+ ELSE
feedback_reg(0) <= (feedback_reg(6) xor feedback_reg(5) xor feedback_reg(5) xor feedback_reg(4));
feedback_reg(1) <= (feedback_reg(0) xor feedback_reg(6) xor feedback_reg(5));
feedback_reg(2) <= (feedback_reg(1) xor feedback_reg(0));
@@ -84,16 +84,16 @@ begin
feedback_reg(5) <= (feedback_reg(4) xor feedback_reg(3));
feedback_reg(6) <= (feedback_reg(5) xor feedback_reg(4));
feedback_reg(7) <= (feedback_reg(6) xor feedback_reg(5));
- end if;
+ END IF;
- end if;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
err_o <= err_s;
- rdy_o <= '1' when status = Locked else '0';
+ rdy_o <= '1' WHEN status = Locked ELSE '0';
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/hdl/prbs/prbs7_8b_generator.vhd b/hdl/prbs/prbs7_8b_generator.vhd
index 98f088843afc142decd11081361e238f8fc10f3f..3b04d5872316af03cda5624e9bb6819b3716e07d 100644
--- a/hdl/prbs/prbs7_8b_generator.vhd
+++ b/hdl/prbs/prbs7_8b_generator.vhd
@@ -1,13 +1,13 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
-entity prbs7_8b_generator is
- generic(
+ENTITY prbs7_8b_generator IS
+ GENERIC(
INIT_c : in std_logic_vector(7 downto 0)
);
- port (
+ PORT (
reset_i : in std_logic;
clk_i : in std_logic;
clken_i : in std_logic;
@@ -18,34 +18,34 @@ entity prbs7_8b_generator is
prbs_word_o : out std_logic_vector(7 downto 0);
rdy_o : out std_logic
);
-end prbs7_8b_generator;
+END prbs7_8b_generator;
-architecture rtl of prbs7_8b_generator is
- signal feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
- signal prbs_word_s : std_logic_vector(7 downto 0) := INIT_c;
- signal err_pattern_s : std_logic_vector(7 downto 0);
- signal err_cnter_s : unsigned(24 downto 0);
- signal inject_error_s : std_logic;
- signal onceinject_done_s : std_logic;
+ARCHITECTURE rtl OF prbs7_8b_generator IS
+ SIGNAL feedback_reg : std_logic_vector(7 downto 0) := INIT_c;
+ SIGNAL prbs_word_s : std_logic_vector(7 downto 0) := INIT_c;
+ SIGNAL err_pattern_s : std_logic_vector(7 downto 0);
+ SIGNAL err_cnter_s : unsigned(24 downto 0);
+ SIGNAL inject_error_s : std_logic;
+ SIGNAL onceinject_done_s : std_logic;
-begin
+BEGIN
-- PRBS7 equation: x^7 + x^6 + 1
-- LSB first
- prbs7_proc: process(reset_i, clk_i)
- begin
+ prbs7_proc: PROCESS(reset_i, clk_i)
+ BEGIN
- if reset_i = '1' then
+ IF reset_i = '1' THEN
feedback_reg <= INIT_c;
prbs_word_s <= INIT_c;
rdy_o <= '0';
- err_cnter_s <= (others => '0');
- err_pattern_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
+ err_pattern_s <= (OTHERS => '0');
- elsif rising_edge(clk_i) then
+ ELSIF rising_edge(clk_i) THEN
- if clken_i = '1' then
+ IF clken_i = '1' THEN
prbs_word_s <= feedback_reg;
rdy_o <= '1';
@@ -61,28 +61,28 @@ begin
err_pattern_s <= x"00";
- if err_pattern_i /= x"00" then
- if std_logic_vector(err_cnter_s) = rep_delay_i then
- if rep_delay_i /= x"000000" or onceinject_done_s = '0' then
+ IF err_pattern_i /= x"00" THEN
+ IF std_logic_vector(err_cnter_s) = rep_delay_i THEN
+ IF rep_delay_i /= x"000000" or onceinject_done_s = '0' THEN
err_pattern_s <= err_pattern_i;
onceinject_done_s <= '1';
- end if;
+ END IF;
- err_cnter_s <= (others => '0');
+ err_cnter_s <= (OTHERS => '0');
- else
+ ELSE
err_cnter_s <= err_cnter_s + 1;
- end if;
- else
- err_cnter_s <= (others => '0');
+ END IF;
+ ELSE
+ err_cnter_s <= (OTHERS => '0');
onceinject_done_s <= '0';
- end if;
- end if;
+ END IF;
+ END IF;
- end if;
+ END IF;
- end process;
+ END PROCESS;
prbs_word_o <= prbs_word_s xor err_pattern_s;
-end rtl;
\ No newline at end of file
+END rtl;
\ No newline at end of file
diff --git a/mgt/10g24/xlx_ku_mgt_10g24.vhd b/mgt/10g24/xlx_ku_mgt_10g24.vhd
index 2e5fd3c9af58fd4bfca6d136336382f660bb3896..7daaac96637b27d57119aab6107690329726e9f2 100644
--- a/mgt/10g24/xlx_ku_mgt_10g24.vhd
+++ b/mgt/10g24/xlx_ku_mgt_10g24.vhd
@@ -1,25 +1,25 @@
-------------------------------------------------------
--! @file
---! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
+--! @author Julian MENDez <julian.mENDez@cern.ch> (CERN - EP-ESE-BE)
--! @version 6.0
---! @brief GBT-FPGA IP - Device specific transceiver
+--! @brief lpGBT-FPGA IP - Device specIFic transceiver
-------------------------------------------------------
---! IEEE VHDL standard library:
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+--! IEEE VHDL standard LIBRARY:
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vcomponents.all;
--! @brief MGT - Transceiver
--! @details
---! The MGT module provides the interface to the transceivers to send the GBT-links via
---! high speed links (@4.8Gbps)
-entity xlx_ku_mgt_10g24 is
- port (
+--! The MGT module provides the interface to the transceivers to sEND the lpGBT-links via
+--! high speed links (@10.24Gbps)
+ENTITY xlx_ku_mgt_10g24 IS
+ PORT (
--=============--
-- Clocks --
--=============--
@@ -66,21 +66,20 @@ entity xlx_ku_mgt_10g24 is
TXn_o : out std_logic;
TXp_o : out std_logic
);
-end xlx_ku_mgt_10g24;
+END xlx_ku_mgt_10g24;
--! @brief MGT - Transceiver
---! @details The MGT module implements all the logic required to send the GBT frame on high speed
---! links: resets modules for the transceiver, Tx PLL and alignement logic to align the received word with the
---! GBT frame header.
-architecture structural of xlx_ku_mgt_10g24 is
- --================================ Signal Declarations ================================--
+--! @details The MGT module implements all the logic required to sEND the lpGBT frame on high speed
+--! links: resets modules for the transceiver and Tx PLL.
+ARCHITECTURE structural OF xlx_ku_mgt_10g24 IS
+ --================================ SIGNAL Declarations ================================--
COMPONENT xlx_ku_mgt_ip_10g24
PORT (
- gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_USErclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_USErclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_buffbypass_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_buffbypass_rx_start_user_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_buffbypass_rx_start_USEr_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_buffbypass_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_buffbypass_rx_error_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -92,8 +91,8 @@ architecture structural of xlx_ku_mgt_10g24 is
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ gtwiz_USErdata_tx_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ gtwiz_USErdata_rx_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
drpaddr_in : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
drpclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
drpdi_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -129,58 +128,58 @@ architecture structural of xlx_ku_mgt_10g24 is
);
END COMPONENT;
- -- Reset signals
- signal tx_reset_done : std_logic;
- signal tx_rdy_done : std_logic;
- signal txfsm_reset_done : std_logic;
- signal rx_reset_done : std_logic;
- signal rxfsm_reset_done : std_logic;
+ -- Reset SIGNALs
+ SIGNAL tx_reset_done : std_logic;
+ SIGNAL tx_rdy_done : std_logic;
+ SIGNAL txfsm_reset_done : std_logic;
+ SIGNAL rx_reset_done : std_logic;
+ SIGNAL rxfsm_reset_done : std_logic;
- signal rxBuffBypassRst : std_logic;
- signal gtwiz_userclk_rx_active_int : std_logic;
- signal gtwiz_buffbypass_rx_reset_in_s : std_logic;
- signal gtwiz_userclk_tx_active_int : std_logic;
- signal gtwiz_buffbypass_tx_reset_in_s : std_logic;
+ SIGNAL rxBuffBypassRst : std_logic;
+ SIGNAL gtwiz_USErclk_rx_active_int : std_logic;
+ SIGNAL gtwiz_buffbypass_rx_reset_in_s : std_logic;
+ SIGNAL gtwiz_USErclk_tx_active_int : std_logic;
+ SIGNAL gtwiz_buffbypass_tx_reset_in_s : std_logic;
- signal gtwiz_userclk_tx_reset_int : std_logic;
- signal gtwiz_userclk_rx_reset_int : std_logic;
- signal txpmaresetdone : std_logic;
- signal rxpmaresetdone : std_logic;
+ SIGNAL gtwiz_USErclk_tx_reset_int : std_logic;
+ SIGNAL gtwiz_USErclk_rx_reset_int : std_logic;
+ SIGNAL txpmaresetdone : std_logic;
+ SIGNAL rxpmaresetdone : std_logic;
- signal rx_reset_sig : std_logic;
- signal tx_reset_sig : std_logic;
+ SIGNAL rx_reset_sig : std_logic;
+ SIGNAL tx_reset_sig : std_logic;
- signal MGT_USRWORD_s : std_logic_vector(31 downto 0);
+ SIGNAL MGT_USRWORD_s : std_logic_vector(31 downto 0);
- -- Clock signals
- signal rx_wordclk_sig : std_logic;
- signal tx_wordclk_sig : std_logic;
- signal rxoutclk_sig : std_logic;
- signal txoutclk_sig : std_logic;
+ -- Clock SIGNALs
+ SIGNAL rx_wordclk_sig : std_logic;
+ SIGNAL tx_wordclk_sig : std_logic;
+ SIGNAL rxoutclk_sig : std_logic;
+ SIGNAL txoutclk_sig : std_logic;
- -- Tx phase aligner signals
- signal txbufstatus_s : std_logic_vector(1 downto 0);
+ -- Tx phase aligner SIGNALs
+ SIGNAL txbufstatus_s : std_logic_vector(1 downto 0);
- signal txpippmen_s : std_logic;
- signal txpippmovrden_s : std_logic;
- signal txpippmsel_s : std_logic;
- signal txpippmpd_s : std_logic;
- signal txpippmstepsize_in : std_logic_vector(4 downto 0);
+ SIGNAL txpippmen_s : std_logic;
+ SIGNAL txpippmovrden_s : std_logic;
+ SIGNAL txpippmsel_s : std_logic;
+ SIGNAL txpippmpd_s : std_logic;
+ SIGNAL txpippmstepsize_in : std_logic_vector(4 downto 0);
- signal drpaddr_s : std_logic_vector(8 downto 0);
- signal drpen_s : std_logic;
- signal drpdi_s : std_logic_vector(15 downto 0);
- signal drprdy_s : std_logic;
- signal drpdo_s : std_logic_vector(15 downto 0);
- signal drpwe_s : std_logic;
+ SIGNAL drpaddr_s : std_logic_vector(8 downto 0);
+ SIGNAL drpen_s : std_logic;
+ SIGNAL drpdi_s : std_logic_vector(15 downto 0);
+ SIGNAL drprdy_s : std_logic;
+ SIGNAL drpdo_s : std_logic_vector(15 downto 0);
+ SIGNAL drpwe_s : std_logic;
- signal mgt_rst_phaligner_s : std_logic;
- signal MGT_TX_ALIGNED_s : std_logic;
+ SIGNAL mgt_rst_phaligner_s : std_logic;
+ SIGNAL MGT_TX_ALIGNED_s : std_logic;
--=================================================================================================--
-begin --========#### Architecture Body ####========--
+BEGIN --========#### ARCHITECTURE Body ####========--
--=================================================================================================--
- --==================================== User Logic =====================================--
+ --==================================== USEr Logic =====================================--
--=============--
-- Assignments --
@@ -197,9 +196,9 @@ begin --========#### Architecture Body ####========--
rx_reset_sig <= MGT_RXRESET_i or not(tx_reset_done and MGT_TX_ALIGNED_s); -- and txfsm_reset_done);
tx_reset_sig <= MGT_TXRESET_i;
- rxBuffBypassRst <= not(gtwiz_userclk_rx_active_int) or (not(tx_reset_done) and not(MGT_TX_ALIGNED_s));
+ rxBuffBypassRst <= not(gtwiz_USErclk_rx_active_int) or (not(tx_reset_done) and not(MGT_TX_ALIGNED_s));
- resetDoneSynch_rx: entity work.xlx_ku_mgt_ip_reset_synchronizer
+ resetDoneSynch_rx: ENTITY work.xlx_ku_mgt_ip_reset_synchronizer
PORT MAP(
clk_in => rx_wordClk_sig,
rst_in => rxBuffBypassRst,
@@ -207,21 +206,21 @@ begin --========#### Architecture Body ####========--
);
--- resetSynch_tx: entity work.xlx_ku_mgt_ip_reset_synchronizer
+-- resetSynch_tx: ENTITY work.xlx_ku_mgt_ip_reset_synchronizer
-- PORT MAP(
-- clk_in => tx_wordclk_sig,
--- rst_in => not(gtwiz_userclk_tx_active_int),
+-- rst_in => not(gtwiz_USErclk_tx_active_int),
-- rst_out => gtwiz_buffbypass_tx_reset_in_s
-- );
- gtwiz_userclk_tx_reset_int <= not(txpmaresetdone);
- gtwiz_userclk_rx_reset_int <= not(rxpmaresetdone);
+ gtwiz_USErclk_tx_reset_int <= not(txpmaresetdone);
+ gtwiz_USErclk_rx_reset_int <= not(rxpmaresetdone);
rxWordClkBuf_inst: bufg_gt
- port map (
+ PORT MAP (
O => rx_wordclk_sig,
I => rxoutclk_sig,
- CE => not(gtwiz_userclk_rx_reset_int),
+ CE => not(gtwiz_USErclk_rx_reset_int),
DIV => "000",
CLR => '0',
CLRMASK => '0',
@@ -229,45 +228,45 @@ begin --========#### Architecture Body ####========--
);
txWordClkBuf_inst: bufg_gt
- port map (
+ PORT MAP (
O => tx_wordclk_sig,
I => txoutclk_sig,
- CE => not(gtwiz_userclk_tx_reset_int),
+ CE => not(gtwiz_USErclk_tx_reset_int),
DIV => "000",
CLR => '0',
CLRMASK => '0',
CEMASK => '0'
);
- activetxUsrClk_proc: process(gtwiz_userclk_tx_reset_int, tx_wordclk_sig)
- begin
- if gtwiz_userclk_tx_reset_int = '1' then
- gtwiz_userclk_tx_active_int <= '0';
- elsif rising_edge(tx_wordclk_sig) then
- gtwiz_userclk_tx_active_int <= '1';
- end if;
+ activetxUsrClk_proc: PROCESS(gtwiz_USErclk_tx_reset_int, tx_wordclk_sig)
+ BEGIN
+ IF gtwiz_USErclk_tx_reset_int = '1' THEN
+ gtwiz_USErclk_tx_active_int <= '0';
+ ELSIF rising_edge(tx_wordclk_sig) THEN
+ gtwiz_USErclk_tx_active_int <= '1';
+ END IF;
- end process;
+ END PROCESS;
- activerxUsrClk_proc: process(gtwiz_userclk_rx_reset_int, rx_wordclk_sig)
- begin
- if gtwiz_userclk_rx_reset_int = '1' then
- gtwiz_userclk_rx_active_int <= '0';
- elsif rising_edge(rx_wordclk_sig) then
- gtwiz_userclk_rx_active_int <= '1';
- end if;
+ activerxUsrClk_proc: PROCESS(gtwiz_USErclk_rx_reset_int, rx_wordclk_sig)
+ BEGIN
+ IF gtwiz_USErclk_rx_reset_int = '1' THEN
+ gtwiz_USErclk_rx_active_int <= '0';
+ ELSIF rising_edge(rx_wordclk_sig) THEN
+ gtwiz_USErclk_rx_active_int <= '1';
+ END IF;
- end process;
+ END PROCESS;
- rxWordPipeline_proc: process(rx_reset_done, rx_wordclk_sig)
- begin
- if rx_reset_done = '0' then
- MGT_USRWORD_o <= (others => '0');
- elsif rising_edge(rx_wordclk_sig) then
+ rxWordPipeline_proc: PROCESS(rx_reset_done, rx_wordclk_sig)
+ BEGIN
+ IF rx_reset_done = '0' THEN
+ MGT_USRWORD_o <= (OTHERS => '0');
+ ELSIF rising_edge(rx_wordclk_sig) THEN
MGT_USRWORD_o <= MGT_USRWORD_s;
- end if;
- end process;
+ END IF;
+ END PROCESS;
xlx_ku_mgt_std_i: xlx_ku_mgt_ip_10g24
@@ -279,16 +278,16 @@ begin --========#### Architecture Body ####========--
txusrclk2_in(0) => tx_wordclk_sig,
txoutclk_out(0) => txoutclk_sig,
- gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_int,
- gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_int,
+ gtwiz_USErclk_tx_active_in(0) => gtwiz_USErclk_tx_active_int,
+ gtwiz_USErclk_rx_active_in(0) => gtwiz_USErclk_rx_active_int,
--gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in_s,
- --gtwiz_buffbypass_tx_start_user_in(0) => '0',
+ --gtwiz_buffbypass_tx_start_USEr_in(0) => '0',
--gtwiz_buffbypass_tx_done_out(0) => txfsm_reset_done,
--gtwiz_buffbypass_tx_error_out => open,
gtwiz_buffbypass_rx_reset_in(0) => gtwiz_buffbypass_rx_reset_in_s,
- gtwiz_buffbypass_rx_start_user_in(0) => '0',
+ gtwiz_buffbypass_rx_start_USEr_in(0) => '0',
gtwiz_buffbypass_rx_done_out(0) => rxfsm_reset_done,
gtwiz_buffbypass_rx_error_out => open,
@@ -304,8 +303,8 @@ begin --========#### Architecture Body ####========--
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_rx_done_out(0) => rx_reset_done,
- gtwiz_userdata_tx_in => MGT_USRWORD_i,
- gtwiz_userdata_rx_out => MGT_USRWORD_s,
+ gtwiz_USErdata_tx_in => MGT_USRWORD_i,
+ gtwiz_USErdata_rx_out => MGT_USRWORD_s,
drpclk_in(0) => MGT_FREEDRPCLK_i,
@@ -321,7 +320,7 @@ begin --========#### Architecture Body ####========--
rxpmaresetdone_out(0) => rxpmaresetdone,
txpmaresetdone_out(0) => txpmaresetdone,
- -- DRP bus (used by the tx phase aligner)
+ -- DRP bus (USEd by the tx phase aligner)
drpaddr_in => drpaddr_s,
drpdi_in => drpdi_s,
drpen_in(0) => drpen_s,
@@ -329,7 +328,7 @@ begin --========#### Architecture Body ####========--
drpdo_out => drpdo_s,
drprdy_out(0) => drprdy_s,
- -- PI control / monitoring signals
+ -- PI control / monitoring SIGNALs
txpippmen_in(0) => txpippmen_s,
txpippmovrden_in(0) => txpippmovrden_s,
txpippmpd_in(0) => txpippmpd_s,
@@ -351,15 +350,15 @@ begin --========#### Architecture Body ####========--
txpippmovrden_s <= '0';
txpippmsel_s <= '0';
txpippmpd_s <= '0';
- txpippmstepsize_in <= (others => '0');
+ txpippmstepsize_in <= (OTHERS => '0');
- drpaddr_s <= (others => '0');
+ drpaddr_s <= (OTHERS => '0');
drpen_s <= '0';
- drpdi_s <= (others => '0');
+ drpdi_s <= (OTHERS => '0');
drpwe_s <= '0';
MGT_TX_ALIGNED_s <= tx_reset_done;
-end structural;
+END structural;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
diff --git a/mgt/5g12/xlx_ku_mgt_5g12.vhd b/mgt/5g12/xlx_ku_mgt_5g12.vhd
index e3dae7f4f3edc88ca2881b462adaf3b783b9673d..2bf471e44170ac7b22b8e8773b842df36a2a814e 100644
--- a/mgt/5g12/xlx_ku_mgt_5g12.vhd
+++ b/mgt/5g12/xlx_ku_mgt_5g12.vhd
@@ -1,25 +1,25 @@
-------------------------------------------------------
--! @file
---! @author Julian Mendez <julian.mendez@cern.ch> (CERN - EP-ESE-BE)
---! @version 6.0
---! @brief GBT-FPGA IP - Device specific transceiver
+--! @author Julian MENDez <julian.mENDez@cern.ch> (CERN - EP-ESE-BE)
+--! @version 2.0
+--! @brief lpGBT-FPGA IP - Device specIFic transceiver
-------------------------------------------------------
---! IEEE VHDL standard library:
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
+--! IEEE VHDL standard LIBRARY:
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
---! Xilinx devices library:
-library unisim;
-use unisim.vcomponents.all;
+--! Xilinx devices LIBRARY:
+LIBRARY unisim;
+USE unisim.vcomponents.all;
--! @brief MGT - Transceiver
--! @details
---! The MGT module provides the interface to the transceivers to send the GBT-links via
---! high speed links (@4.8Gbps)
-entity xlx_ku_mgt_5g12 is
- port (
+--! The MGT module provides the interface to the transceivers to sEND the lpGBT-links via
+--! high speed links (@5.12Gbps)
+ENTITY xlx_ku_mgt_5g12 IS
+ PORT (
--=============--
-- Clocks --
--=============--
@@ -66,21 +66,20 @@ entity xlx_ku_mgt_5g12 is
TXn_o : out std_logic;
TXp_o : out std_logic
);
-end xlx_ku_mgt_5g12;
+END xlx_ku_mgt_5g12;
--! @brief MGT - Transceiver
---! @details The MGT module implements all the logic required to send the GBT frame on high speed
---! links: resets modules for the transceiver, Tx PLL and alignement logic to align the received word with the
---! GBT frame header.
-architecture structural of xlx_ku_mgt_5g12 is
- --================================ Signal Declarations ================================--
+--! @details The MGT module implements all the logic required to sEND the lpGBT frame on high speed
+--! links: resets modules for the transceiver and Tx PLL
+ARCHITECTURE structural OF xlx_ku_mgt_5g12 IS
+ --================================ SIGNAL Declarations ================================--
COMPONENT xlx_ku_mgt_ip_5g12
PORT (
- gtwiz_userclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_USErclk_tx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_USErclk_rx_active_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_buffbypass_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_buffbypass_rx_start_user_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_buffbypass_rx_start_USEr_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_buffbypass_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_buffbypass_rx_error_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
@@ -92,8 +91,8 @@ architecture structural of xlx_ku_mgt_5g12 is
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ gtwiz_USErdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ gtwiz_USErdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
drpaddr_in : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
drpclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
drpdi_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
@@ -128,58 +127,58 @@ architecture structural of xlx_ku_mgt_5g12 is
);
END COMPONENT;
- -- Reset signals
- signal tx_reset_done : std_logic;
- signal tx_rdy_done : std_logic;
- signal txfsm_reset_done : std_logic;
- signal rx_reset_done : std_logic;
- signal rxfsm_reset_done : std_logic;
+ -- Reset SIGNALs
+ SIGNAL tx_reset_done : std_logic;
+ SIGNAL tx_rdy_done : std_logic;
+ SIGNAL txfsm_reset_done : std_logic;
+ SIGNAL rx_reset_done : std_logic;
+ SIGNAL rxfsm_reset_done : std_logic;
- signal rxBuffBypassRst : std_logic;
- signal gtwiz_userclk_rx_active_int : std_logic;
- signal gtwiz_buffbypass_rx_reset_in_s : std_logic;
- signal gtwiz_userclk_tx_active_int : std_logic;
- signal gtwiz_buffbypass_tx_reset_in_s : std_logic;
+ SIGNAL rxBuffBypassRst : std_logic;
+ SIGNAL gtwiz_USErclk_rx_active_int : std_logic;
+ SIGNAL gtwiz_buffbypass_rx_reset_in_s : std_logic;
+ SIGNAL gtwiz_USErclk_tx_active_int : std_logic;
+ SIGNAL gtwiz_buffbypass_tx_reset_in_s : std_logic;
- signal gtwiz_userclk_tx_reset_int : std_logic;
- signal gtwiz_userclk_rx_reset_int : std_logic;
- signal txpmaresetdone : std_logic;
- signal rxpmaresetdone : std_logic;
+ SIGNAL gtwiz_USErclk_tx_reset_int : std_logic;
+ SIGNAL gtwiz_USErclk_rx_reset_int : std_logic;
+ SIGNAL txpmaresetdone : std_logic;
+ SIGNAL rxpmaresetdone : std_logic;
- signal rx_reset_sig : std_logic;
- signal tx_reset_sig : std_logic;
+ SIGNAL rx_reset_sig : std_logic;
+ SIGNAL tx_reset_sig : std_logic;
- signal MGT_USRWORD_s : std_logic_vector(15 downto 0);
+ SIGNAL MGT_USRWORD_s : std_logic_vector(15 downto 0);
- -- Clock signals
- signal rx_wordclk_sig : std_logic;
- signal tx_wordclk_sig : std_logic;
- signal rxoutclk_sig : std_logic;
- signal txoutclk_sig : std_logic;
+ -- Clock SIGNALs
+ SIGNAL rx_wordclk_sig : std_logic;
+ SIGNAL tx_wordclk_sig : std_logic;
+ SIGNAL rxoutclk_sig : std_logic;
+ SIGNAL txoutclk_sig : std_logic;
- -- Tx phase aligner signals
- signal txbufstatus_s : std_logic_vector(1 downto 0);
+ -- Tx phase aligner SIGNALs
+ SIGNAL txbufstatus_s : std_logic_vector(1 downto 0);
- signal txpippmen_s : std_logic;
- signal txpippmovrden_s : std_logic;
- signal txpippmsel_s : std_logic;
- signal txpippmpd_s : std_logic;
- signal txpippmstepsize_in : std_logic_vector(4 downto 0);
+ SIGNAL txpippmen_s : std_logic;
+ SIGNAL txpippmovrden_s : std_logic;
+ SIGNAL txpippmsel_s : std_logic;
+ SIGNAL txpippmpd_s : std_logic;
+ SIGNAL txpippmstepsize_in : std_logic_vector(4 downto 0);
- signal drpaddr_s : std_logic_vector(8 downto 0);
- signal drpen_s : std_logic;
- signal drpdi_s : std_logic_vector(15 downto 0);
- signal drprdy_s : std_logic;
- signal drpdo_s : std_logic_vector(15 downto 0);
- signal drpwe_s : std_logic;
+ SIGNAL drpaddr_s : std_logic_vector(8 downto 0);
+ SIGNAL drpen_s : std_logic;
+ SIGNAL drpdi_s : std_logic_vector(15 downto 0);
+ SIGNAL drprdy_s : std_logic;
+ SIGNAL drpdo_s : std_logic_vector(15 downto 0);
+ SIGNAL drpwe_s : std_logic;
- signal mgt_rst_phaligner_s : std_logic;
- signal MGT_TX_ALIGNED_s : std_logic;
+ SIGNAL mgt_rst_phaligner_s : std_logic;
+ SIGNAL MGT_TX_ALIGNED_s : std_logic;
--=================================================================================================--
-begin --========#### Architecture Body ####========--
+BEGIN --========#### ARCHITECTURE Body ####========--
--=================================================================================================--
- --==================================== User Logic =====================================--
+ --==================================== USEr Logic =====================================--
--=============--
-- Assignments --
@@ -196,9 +195,9 @@ begin --========#### Architecture Body ####========--
rx_reset_sig <= MGT_RXRESET_i or not(tx_reset_done and MGT_TX_ALIGNED_s); -- and txfsm_reset_done);
tx_reset_sig <= MGT_TXRESET_i;
- rxBuffBypassRst <= not(gtwiz_userclk_rx_active_int) or (not(tx_reset_done) and not(MGT_TX_ALIGNED_s));
+ rxBuffBypassRst <= not(gtwiz_USErclk_rx_active_int) or (not(tx_reset_done) and not(MGT_TX_ALIGNED_s));
- resetDoneSynch_rx: entity work.xlx_ku_mgt_ip_reset_synchronizer
+ resetDoneSynch_rx: ENTITY work.xlx_ku_mgt_ip_reset_synchronizer
PORT MAP(
clk_in => rx_wordClk_sig,
rst_in => rxBuffBypassRst,
@@ -206,21 +205,21 @@ begin --========#### Architecture Body ####========--
);
--- resetSynch_tx: entity work.xlx_ku_mgt_ip_reset_synchronizer
+-- resetSynch_tx: ENTITY work.xlx_ku_mgt_ip_reset_synchronizer
-- PORT MAP(
-- clk_in => tx_wordclk_sig,
--- rst_in => not(gtwiz_userclk_tx_active_int),
+-- rst_in => not(gtwiz_USErclk_tx_active_int),
-- rst_out => gtwiz_buffbypass_tx_reset_in_s
-- );
- gtwiz_userclk_tx_reset_int <= not(txpmaresetdone);
- gtwiz_userclk_rx_reset_int <= not(rxpmaresetdone);
+ gtwiz_USErclk_tx_reset_int <= not(txpmaresetdone);
+ gtwiz_USErclk_rx_reset_int <= not(rxpmaresetdone);
rxWordClkBuf_inst: bufg_gt
- port map (
+ PORT MAP (
O => rx_wordclk_sig,
I => rxoutclk_sig,
- CE => not(gtwiz_userclk_rx_reset_int),
+ CE => not(gtwiz_USErclk_rx_reset_int),
DIV => "000",
CLR => '0',
CLRMASK => '0',
@@ -228,45 +227,45 @@ begin --========#### Architecture Body ####========--
);
txWordClkBuf_inst: bufg_gt
- port map (
+ PORT MAP (
O => tx_wordclk_sig,
I => txoutclk_sig,
- CE => not(gtwiz_userclk_tx_reset_int),
+ CE => not(gtwiz_USErclk_tx_reset_int),
DIV => "000",
CLR => '0',
CLRMASK => '0',
CEMASK => '0'
);
- activetxUsrClk_proc: process(gtwiz_userclk_tx_reset_int, tx_wordclk_sig)
- begin
- if gtwiz_userclk_tx_reset_int = '1' then
- gtwiz_userclk_tx_active_int <= '0';
- elsif rising_edge(tx_wordclk_sig) then
- gtwiz_userclk_tx_active_int <= '1';
- end if;
+ activetxUsrClk_proc: PROCESS(gtwiz_USErclk_tx_reset_int, tx_wordclk_sig)
+ BEGIN
+ IF gtwiz_USErclk_tx_reset_int = '1' THEN
+ gtwiz_USErclk_tx_active_int <= '0';
+ ELSIF rising_edge(tx_wordclk_sig) THEN
+ gtwiz_USErclk_tx_active_int <= '1';
+ END IF;
- end process;
+ END PROCESS;
- activerxUsrClk_proc: process(gtwiz_userclk_rx_reset_int, rx_wordclk_sig)
- begin
- if gtwiz_userclk_rx_reset_int = '1' then
- gtwiz_userclk_rx_active_int <= '0';
- elsif rising_edge(rx_wordclk_sig) then
- gtwiz_userclk_rx_active_int <= '1';
- end if;
+ activerxUsrClk_proc: PROCESS(gtwiz_USErclk_rx_reset_int, rx_wordclk_sig)
+ BEGIN
+ IF gtwiz_USErclk_rx_reset_int = '1' THEN
+ gtwiz_USErclk_rx_active_int <= '0';
+ ELSIF rising_edge(rx_wordclk_sig) THEN
+ gtwiz_USErclk_rx_active_int <= '1';
+ END IF;
- end process;
+ END PROCESS;
- rxWordPipeline_proc: process(rx_reset_done, rx_wordclk_sig)
- begin
- if rx_reset_done = '0' then
- MGT_USRWORD_o <= (others => '0');
- elsif rising_edge(rx_wordclk_sig) then
+ rxWordPipeline_proc: PROCESS(rx_reset_done, rx_wordclk_sig)
+ BEGIN
+ IF rx_reset_done = '0' THEN
+ MGT_USRWORD_o <= (OTHERS => '0');
+ ELSIF rising_edge(rx_wordclk_sig) THEN
MGT_USRWORD_o <= MGT_USRWORD_s;
- end if;
- end process;
+ END IF;
+ END PROCESS;
xlx_ku_mgt_std_i: xlx_ku_mgt_ip_5g12
@@ -278,16 +277,16 @@ begin --========#### Architecture Body ####========--
txusrclk2_in(0) => tx_wordclk_sig,
txoutclk_out(0) => txoutclk_sig,
- gtwiz_userclk_tx_active_in(0) => gtwiz_userclk_tx_active_int,
- gtwiz_userclk_rx_active_in(0) => gtwiz_userclk_rx_active_int,
+ gtwiz_USErclk_tx_active_in(0) => gtwiz_USErclk_tx_active_int,
+ gtwiz_USErclk_rx_active_in(0) => gtwiz_USErclk_rx_active_int,
--gtwiz_buffbypass_tx_reset_in(0) => gtwiz_buffbypass_tx_reset_in_s,
- --gtwiz_buffbypass_tx_start_user_in(0) => '0',
+ --gtwiz_buffbypass_tx_start_USEr_in(0) => '0',
--gtwiz_buffbypass_tx_done_out(0) => txfsm_reset_done,
--gtwiz_buffbypass_tx_error_out => open,
gtwiz_buffbypass_rx_reset_in(0) => gtwiz_buffbypass_rx_reset_in_s,
- gtwiz_buffbypass_rx_start_user_in(0) => '0',
+ gtwiz_buffbypass_rx_start_USEr_in(0) => '0',
gtwiz_buffbypass_rx_done_out(0) => rxfsm_reset_done,
gtwiz_buffbypass_rx_error_out => open,
@@ -303,8 +302,8 @@ begin --========#### Architecture Body ####========--
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_rx_done_out(0) => rx_reset_done,
- gtwiz_userdata_tx_in => MGT_USRWORD_i,
- gtwiz_userdata_rx_out => MGT_USRWORD_s,
+ gtwiz_USErdata_tx_in => MGT_USRWORD_i,
+ gtwiz_USErdata_rx_out => MGT_USRWORD_s,
drpclk_in(0) => MGT_FREEDRPCLK_i,
@@ -320,7 +319,7 @@ begin --========#### Architecture Body ####========--
rxpmaresetdone_out(0) => rxpmaresetdone,
txpmaresetdone_out(0) => txpmaresetdone,
- -- DRP bus (used by the tx phase aligner)
+ -- DRP bus (USEd by the tx phase aligner)
drpaddr_in => drpaddr_s,
drpdi_in => drpdi_s,
drpen_in(0) => drpen_s,
@@ -328,7 +327,7 @@ begin --========#### Architecture Body ####========--
drpdo_out => drpdo_s,
drprdy_out(0) => drprdy_s,
- -- PI control / monitoring signals
+ -- PI control / monitoring SIGNALs
txpippmen_in(0) => txpippmen_s,
txpippmovrden_in(0) => txpippmovrden_s,
txpippmpd_in(0) => txpippmpd_s,
@@ -349,15 +348,15 @@ begin --========#### Architecture Body ####========--
txpippmovrden_s <= '0';
txpippmsel_s <= '0';
txpippmpd_s <= '0';
- txpippmstepsize_in <= (others => '0');
+ txpippmstepsize_in <= (OTHERS => '0');
- drpaddr_s <= (others => '0');
+ drpaddr_s <= (OTHERS => '0');
drpen_s <= '0';
- drpdi_s <= (others => '0');
+ drpdi_s <= (OTHERS => '0');
drpwe_s <= '0';
MGT_TX_ALIGNED_s <= tx_reset_done;
-end structural;
+END structural;
--=================================================================================================--
--#################################################################################################--
--=================================================================================================--
\ No newline at end of file
diff --git a/mgt/xlx_ku_mgt_ip_reset_synchronizer.vhd b/mgt/xlx_ku_mgt_ip_reset_synchronizer.vhd
index e570ae3aaeabc49941123465ae2f148fa888512b..ec0dd01476944bebdcdaf7c3203dcc090010c92d 100644
--- a/mgt/xlx_ku_mgt_ip_reset_synchronizer.vhd
+++ b/mgt/xlx_ku_mgt_ip_reset_synchronizer.vhd
@@ -6,49 +6,49 @@
-------------------------------------------------------
--! IEEE VHDL standard library:
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
--! @brief xlx_ku_mgt_ip_reset_synchronizer - Transceiver reset synchronizer
--! @details
--! The xlx_ku_mgt_ip_reset_synchronizer synchronizes the resets with a specific clock domain
-entity xlx_ku_mgt_ip_reset_synchronizer is
- port (
+ENTITY xlx_ku_mgt_ip_reset_synchronizer IS
+ PORT (
CLK_IN : in std_logic;
RST_IN : in std_logic;
RST_OUT : out std_logic
);
-end xlx_ku_mgt_ip_reset_synchronizer;
+END xlx_ku_mgt_ip_reset_synchronizer;
--! @brief xlx_ku_mgt_ip_reset_synchronizer - Transceiver reset
--! @details The xlx_ku_mgt_ip_reset_synchronizer implements a reset bridge system
-architecture Behavioral of xlx_ku_mgt_ip_reset_synchronizer is
+ARCHITECTURE Behavioral OF xlx_ku_mgt_ip_reset_synchronizer IS
- signal rst_in_meta: std_logic;
- signal rst_in_sync1: std_logic;
- signal rst_in_sync2: std_logic;
- signal rst_in_sync3: std_logic;
- signal rst_in_out: std_logic;
+ SIGNAL rst_in_meta: std_logic;
+ SIGNAL rst_in_sync1: std_logic;
+ SIGNAL rst_in_sync2: std_logic;
+ SIGNAL rst_in_sync3: std_logic;
+ SIGNAL rst_in_out: std_logic;
-begin
+BEGIN
- rstFsm_proc: process(clk_in, rst_in)
- begin
- if rst_in = '1' then
+ rstFsm_proc: PROCESS(clk_in, rst_in)
+ BEGIN
+ IF rst_in = '1' THEN
rst_in_meta <= '1';
rst_in_sync1 <= '1';
rst_in_sync2 <= '1';
rst_in_sync3 <= '1';
rst_in_out <= '1';
- elsif rising_edge(clk_in) then
+ ELSIF rising_edge(clk_in) THEN
rst_in_meta <= '0';
rst_in_sync1 <= rst_in_meta;
rst_in_sync2 <= rst_in_sync1;
rst_in_sync3 <= rst_in_sync2;
rst_in_out <= rst_in_sync3;
- end if;
- end process;
+ END IF;
+ END PROCESS;
rst_out <= rst_in_out;
-end Behavioral;
+END Behavioral;