Caribou issueshttps://gitlab.cern.ch/groups/Caribou/-/issues2024-03-20T17:39:57+01:00https://gitlab.cern.ch/Caribou/boreal/-/issues/1CI doesn't fail when cocotb simulation fails2024-03-20T17:39:57+01:00Younes OtaridCI doesn't fail when cocotb simulation failsAs the cocotb simulation implements a soft process exit when the simulation fails, the CI job doesn't catch a process failure and thus doesn't report the failure in the workflow. The CI therefore succeeds even if the simulation fails.As the cocotb simulation implements a soft process exit when the simulation fails, the CI job doesn't catch a process failure and thus doesn't report the failure in the workflow. The CI therefore succeeds even if the simulation fails.Younes OtaridYounes Otaridhttps://gitlab.cern.ch/Caribou/peary/-/issues/31Implement reading of bias voltage on the CaR board2022-03-02T01:50:44+01:00Tomas VanatImplement reading of bias voltage on the CaR boardIt would be useful to have a function/command to check what is the current BIAS_* voltage. There is not a way how to measure the real voltage but it should be enough to return the value that was set.It would be useful to have a function/command to check what is the current BIAS_* voltage. There is not a way how to measure the real voltage but it should be enough to return the value that was set.https://gitlab.cern.ch/Caribou/peary/-/issues/29Issue in Caribou Bild with C10042021-12-16T12:25:57+01:00Simon SpannagelIssue in Caribou Bild with C1004```
C1004/C1004Device.cpp:39:27: error: no matching function for call to 'caribou::dictionary<std::pair<caribou::memory_map, caribou::register_t<unsigned int, unsigned int> > >::add(<brace-enclosed initializer list>)'
| 39 | _memory...```
C1004/C1004Device.cpp:39:27: error: no matching function for call to 'caribou::dictionary<std::pair<caribou::memory_map, caribou::register_t<unsigned int, unsigned int> > >::add(<brace-enclosed initializer list>)'
| 39 | _memory.add(C1004_MEMORY);
| | ^
```
see https://gitlab.cern.ch/Caribou/meta-caribou/-/jobs/18364277Adrian FiergolskiAdrian Fiergolskihttps://gitlab.cern.ch/Caribou/meta-caribou/-/issues/4Configure users at build time2021-05-31T08:32:46+02:00Simon SpannagelConfigure users at build timeuse `extrausers` package and `EXTRA_USERS_PARAM` for configuration on image level.
https://wiki.yoctoproject.org/wiki/FAQ:How_do_I_set_or_change_the_root_password
https://www.yoctoproject.org/pipermail/yocto/2015-April/024610.html
htt...use `extrausers` package and `EXTRA_USERS_PARAM` for configuration on image level.
https://wiki.yoctoproject.org/wiki/FAQ:How_do_I_set_or_change_the_root_password
https://www.yoctoproject.org/pipermail/yocto/2015-April/024610.html
https://git.yoctoproject.org/cgit.cgi/poky/plain/meta/classes/extrausers.bbclassLennart HuthLennart Huthhttps://gitlab.cern.ch/Caribou/peary/-/issues/23Move CaR specific methods from HAL to carboard.2021-04-27T16:19:45+02:00Adrian FiergolskiMove CaR specific methods from HAL to carboard.HAL still contains CaR specific methods (e.g. *SI5345, *Pulser).HAL still contains CaR specific methods (e.g. *SI5345, *Pulser).Simon SpannagelSimon Spannagelhttps://gitlab.cern.ch/Caribou/peary/-/issues/17group DACs and ADCs in a respective common maps2020-05-18T17:56:38+02:00Adrian Fiergolskigroup DACs and ADCs in a respective common mapshttps://gitlab.cern.ch/Caribou/peary/-/issues/13Safety: Make sure default output voltages are zero2019-06-21T14:27:12+02:00Simon SpannagelSafety: Make sure default output voltages are zeroCurrently
```
pearycli
$ switchOn vddd 0
```
produces 3.5V, should be 0V.
Initialize DACs in HAL constructor.Currently
```
pearycli
$ switchOn vddd 0
```
produces 3.5V, should be 0V.
Initialize DACs in HAL constructor.Simon SpannagelSimon Spannagelhttps://gitlab.cern.ch/Caribou/peary/-/issues/8Change of ExampleDevice broke device creation script2022-02-01T15:23:16+01:00Simon SpannagelChange of ExampleDevice broke device creation scriptThe change of the example device merged in !24 broke the script to create a new (Peary) device:
https://gitlab.cern.ch/Caribou/peary/blob/master/etc/scripts/make_device.sh
This should be fixed at some point.
Notify @msmkThe change of the example device merged in !24 broke the script to create a new (Peary) device:
https://gitlab.cern.ch/Caribou/peary/blob/master/etc/scripts/make_device.sh
This should be fixed at some point.
Notify @msmkhttps://gitlab.cern.ch/Caribou/peary/-/issues/6Enable tab completion for dispatcher commands2018-07-31T17:57:49+02:00Simon SpannagelEnable tab completion for dispatcher commandsSimon SpannagelSimon Spannagelhttps://gitlab.cern.ch/Caribou/hardware/chipboards/Caribou-HW-CLICpix2_C3PD/-/issues/2test pads to debug SPI2021-02-03T14:22:45+01:00Adrian Fiergolskitest pads to debug SPITest pads could be added on SPI lines in order to facilitate debugging.
To be addressed in a new design production (if ever).Test pads could be added on SPI lines in order to facilitate debugging.
To be addressed in a new design production (if ever).Iraklis KremastiotisIraklis Kremastiotishttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/15Differential I2C2022-09-01T16:39:44+02:00Adrian FiergolskiDifferential I2CConfirm that differential I2C works (for different Vadj voltage).Confirm that differential I2C works (for different Vadj voltage).Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/14Vadj voltage2022-09-01T16:39:57+02:00Adrian FiergolskiVadj voltageConfirm that CaR board is not sensitive to the different Vadj voltages (2.5V, 1.8V) from the FPGA board.
ZC706 has default Vadj=2.5V.
ZCU102 has default Vadj=1.8V.Confirm that CaR board is not sensitive to the different Vadj voltages (2.5V, 1.8V) from the FPGA board.
ZC706 has default Vadj=2.5V.
ZCU102 has default Vadj=1.8V.Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/13TBD: switch off all the LEDs2022-09-01T16:40:03+02:00Adrian FiergolskiTBD: switch off all the LEDsTo be discussed: It may be required in case of light sensitive devices.To be discussed: It may be required in case of light sensitive devices.Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/12TLU_clk2022-09-01T16:40:08+02:00Adrian FiergolskiTLU_clkTLU_clk to FPGA is missing AC capacitors. It would also enable to disconnect this path completely, in case TLU_clk is used by the Si5345 chip.TLU_clk to FPGA is missing AC capacitors. It would also enable to disconnect this path completely, in case TLU_clk is used by the Si5345 chip.Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/11AC coupling of differential clocks2022-09-01T16:40:12+02:00Adrian FiergolskiAC coupling of differential clocksXilinx recommends an AC coupling of differential clocks coming to FPGA (especially the transceiver reference clocks).Xilinx recommends an AC coupling of differential clocks coming to FPGA (especially the transceiver reference clocks).Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/10mixed power domains2022-09-01T16:40:17+02:00Adrian Fiergolskimixed power domainsAll voltages used to generate a given power domain should be independent.
Hypothetical example:
if during operation, U16 fails, then PWR_ADJ_1 is low and U31 provides maximum voltage damaging DUT.All voltages used to generate a given power domain should be independent.
Hypothetical example:
if during operation, U16 fails, then PWR_ADJ_1 is low and U31 provides maximum voltage damaging DUT.Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/9dynamic control of DC/DC converters2022-09-01T16:40:29+02:00Adrian Fiergolskidynamic control of DC/DC convertersWe can drive LTM_VPWR1_CTR in range 0-4V, which translates to ~3.3V on LTM1_VFB1 (maximum rating is 2.7V). Moreover, DC/DC converter enforces on this node 0.8V. Maybe it would be better to use digital potentiometer powered by some LDO po...We can drive LTM_VPWR1_CTR in range 0-4V, which translates to ~3.3V on LTM1_VFB1 (maximum rating is 2.7V). Moreover, DC/DC converter enforces on this node 0.8V. Maybe it would be better to use digital potentiometer powered by some LDO powered further by the fixed voltage LTM_VCC5?Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/8Dynamic configuration of LDO2022-09-01T16:40:34+02:00Adrian FiergolskiDynamic configuration of LDOIn case DAC provides around 2.8V to PWR_ADJ, the LDO may provide unintentionally the full voltage ([dac.pdf](/uploads/0ee2e4420ff34da8400f313e16eb08a9/dac.pdf) --- slide of Edinei Santin). Maybe we should use digital potentiometers in th...In case DAC provides around 2.8V to PWR_ADJ, the LDO may provide unintentionally the full voltage ([dac.pdf](/uploads/0ee2e4420ff34da8400f313e16eb08a9/dac.pdf) --- slide of Edinei Santin). Maybe we should use digital potentiometers in this circuit instead of DACs as he suggets?Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/7Load of LDOs2022-09-01T16:40:59+02:00Adrian FiergolskiLoad of LDOsAccording to a note in [U31 data sheet](http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=tps74401&fileType=pdf):
>
When V BIAS and V EN are present and V IN is not supplied, this device outputs approximately
50 μ...According to a note in [U31 data sheet](http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=tps74401&fileType=pdf):
>
When V BIAS and V EN are present and V IN is not supplied, this device outputs approximately
50 μA of current from OUT. Although this condition does not cause any damage to the
device, the output current can charge up the OUT node if total resistance between OUT
and GND (including external feedback resistors) is greater than 10 kΩ.
In CaR 1.1, it's more than 10kΩ and potentially (although in unlikely coincidence), we could damage a DUT chip if this node is charged up.Hongbin LiuHongbin Liuhttps://gitlab.cern.ch/Caribou/hardware/carboard/-/issues/6dynamic range of ADS78282022-09-01T16:41:05+02:00Adrian Fiergolskidynamic range of ADS7828ADS7828 is a 12-bit A/D converter with Vref = 4.096 V set externally through a voltage reference, REF5040, on the CaR board. Hence, it can measure a signal with an accuracy no better than Vref/2 12 = 1 mV.
Often the dynamic range of the ...ADS7828 is a 12-bit A/D converter with Vref = 4.096 V set externally through a voltage reference, REF5040, on the CaR board. Hence, it can measure a signal with an accuracy no better than Vref/2 12 = 1 mV.
Often the dynamic range of the measured signals is much lower (for CLICpix2 0-1.2V) so we could have much better accuracy if Vref was dynamically configurable.Hongbin LiuHongbin Liu