Commit 4554a1ff authored by Georg Auzinger's avatar Georg Auzinger
Browse files

verified that version without Shelf is working, updated readme and the setup.sh script

parent 001c2309
......@@ -118,6 +118,10 @@ Cbc_default_electron# CMS Ph2 ACF (Acquisition & Control Framework)
- simplified Definitions.h
- added an Encode Reg method that can be passed the FE ID instead of decoding it from the CBC id
- merged DQM code from Nov15 beamtest
- 03.03.2016: some updates & additions (v1-32)
- added support for CMS Tk Ph2 Data format (.daq) files generation
- added the option for CMS Tk Ph2 Antenna driver as plugin
- removed the Shelf objects from the code for simplicity
### Setup
......@@ -196,7 +200,7 @@ then
$> sudo yum clean all
$> sudo yum groupinstall uhal
3. Install CERN ROOT: [Instructions](http://root.cern.ch/drupal/content/installing-root-source) - make sure to use "fixed location installation"
3. Install CERN ROOT: [Instructions](https://root.cern.ch/building-root) - make sure to use "fixed location installation"
Note: You may also need to set the environment variables (or source setup.sh):
......
......@@ -2,23 +2,23 @@
<HwDescription>
<BeBoard Id="0" boardType="GLIB">
<connection id="board" uri="ipbusudp-2.0://192.168.000.175:50001" address_table="file://settings/address_table_2CBC.xml" />
<connection id="board" uri="ipbusudp-2.0://192.168.000.162:50001" address_table="file://settings/address_table_2CBC.xml" />
<FW_Version NCbcDataSize="8"/>
<FW_Version NCbcDataSize="4"/>
<Module FeId="0" FMCId="0" ModuleId="0" Status="1">
<!-- <Global_CBC_Register name="VCth"> 0x92 </Global_CBC_Register> -->
<!-- <Global_CBC_Register name="TriggerLatency"> 0x05 </Global_CBC_Register>
-->
<CBC_Files path="./settings/"/>
<CBC_Files path="./Results/Calibration_Hole_04-03-16_15:23/"/>
<CBC Id="0" configfile="FE0CBC0.txt"/>
<CBC Id="1" configfile="FE0CBC1.txt"/>
<CBC Id="2" configfile="FE0CBC2.txt"/>
<!-- <CBC Id="2" configfile="FE0CBC2.txt"/>
<CBC Id="3" configfile="FE0CBC3.txt"/>
<CBC Id="4" configfile="FE0CBC4.txt"/>
<CBC Id="5" configfile="FE0CBC5.txt"/>
<CBC Id="6" configfile="FE0CBC6.txt"/>
<CBC Id="7" configfile="FE0CBC7.txt"/>
<CBC Id="7" configfile="FE0CBC7.txt"/> -->
</Module>
......
......@@ -2,7 +2,7 @@
<HwDescription>
<BeBoard Id="0" boardType="GLIB">
<connection id="board" uri="ipbusudp-2.0://192.168.000.175:50001" address_table="file://settings/address_table_2CBC.xml" />
<connection id="board" uri="ipbusudp-2.0://192.168.000.162:50001" address_table="file://settings/address_table_2CBC.xml" />
<FW_Version NCbcDataSize="4"/>
......
......@@ -10,7 +10,7 @@ export BOOST_LIB=/opt/cactus/lib
export BOOST_INCLUDE=/opt/cactus/include
#ROOT
source /usr/local/bin/thisroot.sh
#source /usr/local/bin/thisroot.sh
#Ph2_ACF
export BASE_DIR=$(pwd)
......
......@@ -11,7 +11,7 @@ void PulseShape::Initialize()
uint32_t cBoardId = cBoard->getBeId();
std::cerr << "cBoardId = " << cBoardId << std::endl;
// we could read the Delay_after_TestPulse Register in a variable
uint32_t cDelayAfterPulse = fBeBoardInterface->ReadBoardReg( cBoard, "COMMISSIONNING_MODE_DEALAY_AFTER_TEST_PULSE" );
uint32_t cDelayAfterPulse = fBeBoardInterface->ReadBoardReg( cBoard, "COMMISSIONNING_MODE_DELAY_AFTER_TEST_PULSE" );
fDelayAfterPulse = cDelayAfterPulse;
std::cout << "actual Delay: " << +cDelayAfterPulse << std::endl;
for ( auto& cFe : cBoard->fModuleVector )
......@@ -256,7 +256,7 @@ void PulseShape::setDelayAndTesGroup( uint32_t pDelay )
std::cout << "cFineDelay: " << +cFineDelay << std::endl;
std::cout << "cCoarseDelay: " << +cCoarseDelay << std::endl;
std::cout << "Current Time: " << +pDelay << std::endl;
BeBoardRegWriter cBeBoardWriter( fBeBoardInterface, "COMMISSIONNING_MODE_DEALAY_AFTER_TEST_PULSE", cCoarseDelay );
BeBoardRegWriter cBeBoardWriter( fBeBoardInterface, "COMMISSIONNING_MODE_DELAY_AFTER_TEST_PULSE", cCoarseDelay );
this->accept( cBeBoardWriter );
CbcRegWriter cWriter( fCbcInterface, "SelTestPulseDel&ChanGroup", to_reg( cFineDelay, fTestGroup ) );
this->accept( cWriter );
......
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