Consider different module configurations

The decoder should handle data-merged streams, where the data of multiple frontends is interleaved. Depending of whether it is used in the SWROD to check for errors (which as far as I know is under debate) it should also be ensured, that the data of frontend chips outputting the data on multiple lanes (Nx1.28 Gbps) can be processed in time. Given that the current estimate for decoding speed is ~1 Gbps (single core) this would require multi-core processing of a single data stream. Both of these cases (or just the first one) could be handled for example in a Decoder class wrapping DecCore.