diff --git a/LArCalorimeter/LArROD/python/LArSCSimpleMakerDefault.py b/LArCalorimeter/LArROD/python/LArSCSimpleMakerDefault.py
new file mode 100644
index 0000000000000000000000000000000000000000..3b09cf3ee5c2c3ced66155f03f6b3f63cceda789
--- /dev/null
+++ b/LArCalorimeter/LArROD/python/LArSCSimpleMakerDefault.py
@@ -0,0 +1,30 @@
+# Copyright (C) 2002-2021 CERN for the benefit of the ATLAS collaboration
+
+from LArROD.LArRODConf import LArSCSimpleMaker as _LArSCSimpleMaker
+from LArROD.LArRODConf import LArSuperCellBCIDEmAlg as _LArSuperCellBCIDEmAlg
+
+class LArSCSimpleMaker(_LArSCSimpleMaker):
+   __slots__ = []
+   def __init__(self,name="LArSCSimpleMaker"):
+     super( LArSCSimpleMaker,self).__init__(name)
+     # bunch of needed stuff to make SuperCells from cells (conditions)
+     from CaloTools.CaloNoiseCondAlg import CaloNoiseCondAlg
+     from AthenaCommon.AlgSequence import AthSequencer
+     CaloNoiseCondAlg(noisetype="electronicNoise")
+     condSeq = AthSequencer("AthCondSeq")
+     from CaloRec.CaloRecConf import CaloNoiseSigmaDiffCondAlg
+     if not hasattr(condSeq,"CaloNoiseSigmaDiffCondAlg"):
+       condSeq+=CaloNoiseSigmaDiffCondAlg()
+     from CaloRec.CaloBCIDAvgAlgDefault import CaloBCIDAvgAlgDefault
+     CaloBCIDAvgAlgDefault()
+     self.SCellContainer="SimpleSCellNoBCID"
+
+class LArSuperCellBCIDEmAlg(_LArSuperCellBCIDEmAlg):
+   __slots__ = []
+   def __init__(self,name="LArSuperCellBCIDEmAlg"):
+     super( LArSuperCellBCIDEmAlg,self).__init__(name)
+     # needed conditions to compensate cells from Super-Cells
+     from CaloRec.CaloBCIDAvgAlgDefault import CaloBCIDAvgAlgDefault
+     CaloBCIDAvgAlgDefault()
+     self.SCellContainerIn="SimpleSCellNoBCID"
+
diff --git a/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py b/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
index be434c8d47785a30495222235cd02256bc8a47fb..c27c47afc543e86cb378d8d8982378c242e7add6 100755
--- a/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
+++ b/Trigger/TrigAlgorithms/TrigCaloRec/python/TrigCaloRecConfig.py
@@ -566,6 +566,18 @@ class TrigCaloClusterMakerMT_EMtopo (TrigCaloClusterMakerMTBase):
         self += emtoposplitter
         self += emtopomoments
 
+class HLTCaloCellSeedLessMaker (_HLTCaloCellMaker):
+    __slots__ = []
+    def __init__(self, name="CaloCellSeedLessFS"):
+        super( HLTCaloCellSeedLessMaker, self ).__init__(name)
+        from TrigT2CaloCommon.CaloDef import setMinimalCaloSetup
+        setMinimalCaloSetup()
+        from AthenaCommon.AppMgr import ServiceMgr as svcMgr
+        self.ExtraInputs=[('TileEMScale','ConditionStore+TileEMScale'),('TileBadChannels','ConditionStore+TileBadChannels')]
+        self.ExtraInputs+=[( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TTEM' ), ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TTHEC' ), ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_TILE' ), ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_FCALEM' ), ( 'IRegSelLUTCondData' , 'ConditionStore+RegSelLUTCondData_FCALHAD' ) ]
+        self.CellsName="SeedLessFS"
+        self.RoIs=''
+        self.TrigDataAccessMT=svcMgr.TrigCaloDataAccessSvc
 
 class HLTCaloCellMaker (_HLTCaloCellMaker):
     __slots__ = []
diff --git a/Trigger/TrigAlgorithms/TrigCaloRec/src/HLTCaloCellMaker.cxx b/Trigger/TrigAlgorithms/TrigCaloRec/src/HLTCaloCellMaker.cxx
index e2251dd8bdacf24d70ea73bfa52e92525339ffa6..1bf531055e95cefdf70750fc11ed72167ebc786d 100644
--- a/Trigger/TrigAlgorithms/TrigCaloRec/src/HLTCaloCellMaker.cxx
+++ b/Trigger/TrigAlgorithms/TrigCaloRec/src/HLTCaloCellMaker.cxx
@@ -34,7 +34,9 @@ HLTCaloCellMaker::HLTCaloCellMaker(const std::string & name, ISvcLocator* pSvcLo
 }
 
 StatusCode HLTCaloCellMaker::initialize() {
-  ATH_CHECK( m_roiCollectionKey.initialize() );
+
+  ATH_CHECK( m_roiCollectionKey.initialize(SG::AllowEmpty) );
+
   if ( m_roiMode )
     ATH_CHECK( m_cellContainerKey.initialize() );
   else
@@ -51,12 +53,22 @@ StatusCode HLTCaloCellMaker::execute( const EventContext& context ) const {
   auto timer = Monitored::Timer("TIME_exec");
   auto clN = Monitored::Scalar  ("Cells_N",-999.0);
 
-  auto roisHandle = SG::makeHandle( m_roiCollectionKey, context );
-  if ( not roisHandle.isValid() ) {
-    ATH_MSG_ERROR("Cell maker did not get a valid RoIs collection");
-    return StatusCode::FAILURE;
+  const bool seedLess = m_roiCollectionKey.empty();
+  const TrigRoiDescriptorCollection* roiCollection; 
+  if (!seedLess){
+    auto roisHandle = SG::makeHandle( m_roiCollectionKey, context );
+    if ( not roisHandle.isValid() ) {
+      ATH_MSG_ERROR("Cell maker did not get a valid RoIs collection");
+      return StatusCode::FAILURE;
+    }
+    roiCollection = roisHandle.cptr();
+  } 
+  else { // it is seedLess
+    TrigRoiDescriptorCollection* roiCol = new TrigRoiDescriptorCollection();
+    TrigRoiDescriptor* FS = new TrigRoiDescriptor(true);
+    roiCol->push_back( FS );
+    roiCollection = const_cast<TrigRoiDescriptorCollection*>(roiCol);
   }
-  const TrigRoiDescriptorCollection* roiCollection = roisHandle.cptr();
   ATH_MSG_DEBUG("Operating on " << roiCollection->size() <<"RoI(s)");
 
   // datahandle 
@@ -133,6 +145,8 @@ StatusCode HLTCaloCellMaker::execute( const EventContext& context ) const {
       auto ss = cellContainer.record( std::move(cdv) );
       ATH_CHECK( ss );
 
+      // we have to take care of this
+      if ( seedLess ) { delete roiCollection; }
       return StatusCode::SUCCESS;
     }
 
@@ -209,5 +223,6 @@ StatusCode HLTCaloCellMaker::execute( const EventContext& context ) const {
 
 
    
+  if ( seedLess ) { delete roiCollection; }
   return StatusCode::SUCCESS;
 }
diff --git a/Trigger/TrigT1/TrigT1CaloFexPerf/python/Rel22L1PerfSequence.py b/Trigger/TrigT1/TrigT1CaloFexPerf/python/Rel22L1PerfSequence.py
index fd151255c224d3cce8a44985191cbddbf30ded9d..035e53990a5ab3e026b0bd935d809e3093269a3e 100644
--- a/Trigger/TrigT1/TrigT1CaloFexPerf/python/Rel22L1PerfSequence.py
+++ b/Trigger/TrigT1/TrigT1CaloFexPerf/python/Rel22L1PerfSequence.py
@@ -14,6 +14,7 @@ def setupRun3L1CaloPerfSequence(
             sequence = AlgSequence(
                 "AthAlgSeq"
             )  # everything is added to the AthAlqSequence (which is then put in front of everything)
+                #"topSequence"
         else:
             sequence = AlgSequence()  # everything is added to the topSequence
 
@@ -51,11 +52,42 @@ def setupRun3L1CaloPerfSequence(
     log.info(simflags._context_name)
     simflags.print_JobProperties("tree&value")
 
+    from AthenaCommon.AlgSequence import AthSequencer
     ## Setup the provider of the SuperCells
     if simflags.Calo.SCellType() == "Pulse":
         # These are fully simulated supercells, from supercell pulse
         # collection is CaloCellContainer#SCell
         SCIn = "SCellnoBCID"
+    elif simflags.Calo.SCellType() == "Emulated":
+
+        # Conversion Service instance 
+        from AthenaCommon.GlobalFlags import globalflags
+        handle_transBS=None
+        if ( globalflags.DataSource == "geant4" ): 
+           from LArCabling.LArCablingAccess import LArFebRodMapping
+           LArFebRodMapping()
+           from TrigT1CaloFexPerf.TransBS_forL1_config import configure_transBS
+           handle_transBS=configure_transBS()
+        from TrigCaloRec.TrigCaloRecConfig import HLTCaloCellSeedLessMaker
+
+        SCIn="SimpleSCell"
+        from LArROD.LArSCSimpleMakerDefault import LArSCSimpleMaker
+        from LArROD.LArSCSimpleMakerDefault import LArSuperCellBCIDEmAlg
+        larscsm = LArSCSimpleMaker()
+        larscsm.CellContainer="SeedLessFS"
+        larscbea = LArSuperCellBCIDEmAlg()
+        larscbea.SCellContainerOut=SCIn
+
+        # get a handle for the super-Cell production part
+        #sCell_sequence = AthSequencer("HLTBeginSeq")
+        sCell_sequence = AlgSequence()
+        if (handle_transBS is not None):
+          sCell_sequence+=handle_transBS
+        sCell_sequence+=HLTCaloCellSeedLessMaker()
+        sCell_sequence+=larscsm
+        sCell_sequence+=larscbea
+     
+        return
     elif simflags.Calo.SCellType() == "BCID":
         # These are fully simulated supercells with applied BCID corrections
         # This is the only kind of supercells where BCID corrections are applied
@@ -78,7 +110,6 @@ def setupRun3L1CaloPerfSequence(
         LVL1__METJWoJPerfFex,
     )
 
-    from AthenaCommon.AlgSequence import AthSequencer
 
     condSequence = AthSequencer("AthCondSeq")
     condSequence += LVL1__JTowerMappingDataCondAlg(
diff --git a/Trigger/TrigT1/TrigT1CaloFexPerf/python/TransBS_forL1_config.py b/Trigger/TrigT1/TrigT1CaloFexPerf/python/TransBS_forL1_config.py
new file mode 100644
index 0000000000000000000000000000000000000000..1ae62429264e4f5a52645f2df3c04a62ac304a28
--- /dev/null
+++ b/Trigger/TrigT1/TrigT1CaloFexPerf/python/TransBS_forL1_config.py
@@ -0,0 +1,35 @@
+# Copyright (C) 2002-2021 CERN for the benefit of the ATLAS collaboration
+
+# a number of configuration jobOptions to be used to build transient BS to
+# be used for accessing cells during RDO accessing step
+
+def configure_transBS():
+
+             from AthenaCommon.AppMgr import ServiceMgr as svcMgr
+             from ByteStreamCnvSvc.ByteStreamCnvSvcConf import ByteStreamCnvSvc
+             svcMgr += ByteStreamCnvSvc()
+             # OutputSvc
+             from ByteStreamCnvSvcBase.ByteStreamCnvSvcBaseConf import ROBDataProviderSvc
+             svcMgr += ROBDataProviderSvc()
+             from ByteStreamCnvSvc.ByteStreamCnvSvcConf import ByteStreamRDP_OutputSvc
+             svcMgr += ByteStreamRDP_OutputSvc()
+             # Properties
+             ByteStreamCnvSvc = svcMgr.ByteStreamCnvSvc
+             ByteStreamCnvSvc.ByteStreamOutputSvc ="ByteStreamRDP_OutputSvc"
+             from AthenaServices.AthenaServicesConf import AthenaOutputStream
+             StreamBS = AthenaOutputStream("StreamBS",EvtConversionSvc = "ByteStreamCnvSvc")
+             StreamBS.ItemList +=["2721#*"]
+             StreamBS.ItemList +=["2927#*"]
+             from ByteStreamCnvSvcBase.ByteStreamCnvSvcBaseConf import ByteStreamAddressProviderSvc
+             svcMgr += ByteStreamAddressProviderSvc()
+
+             svcMgr.ByteStreamAddressProviderSvc.TypeNames += [
+                  "TileCellIDC/TileCellIDC"
+                  ]
+             from AthenaCommon.AppMgr import ToolSvc
+             from LArByteStream.LArByteStreamConfig import LArRawDataContByteStreamToolConfig
+             ToolSvc+=LArRawDataContByteStreamToolConfig(InitializeForWriting=True)
+             from SGComps.SGCompsConf import ProxyProviderSvc
+             svcMgr += ProxyProviderSvc()
+             svcMgr.ProxyProviderSvc.ProviderNames += [ "ByteStreamAddressProviderSvc" ]
+             return StreamBS