diff --git a/proto/tests.py b/proto/tests.py
index 74f1dd066c094c08d576f5fe95b3bdf7cf5b5f0a..b3f75070809862dd80240243f63ae03a0c40f7db 100755
--- a/proto/tests.py
+++ b/proto/tests.py
@@ -19,6 +19,7 @@ import cheby.gena2cheby as gena2cheby
import cheby.wbgen2cheby as wbgen2cheby
import cheby.gen_wbgen_hdl as gen_wbgen_hdl
import cheby.print_regs as print_regs
+import cheby.gen_custom as gen_custom
srcdir = '../testfiles/'
verbose = False
@@ -421,6 +422,22 @@ def test_consts():
if not compare_buffer_and_file(buf, file):
error('consts {} generation error for {}'.format(style, f))
+def test_custom():
+ for f in ['custom/fidsErrMiss']:
+ if verbose:
+ print('test custom: {}'.format(f))
+ cheby_file = srcdir + f + '.cheby'
+ c_file = srcdir + f + '.h'
+ t = parse_ok(cheby_file)
+ layout_ok(t)
+ buf = write_buffer()
+ # We need to change working directory
+ cwd = os.getcwd()
+ os.chdir(srcdir + '/custom')
+ gen_custom.generate_custom(buf, t)
+ os.chdir(cwd)
+ if not compare_buffer_and_file(buf, c_file):
+ error('custom generation error for {}'.format(f))
def main():
global verbose
@@ -442,6 +459,7 @@ def main():
test_gena2cheby_err()
test_wbgen2cheby()
test_consts()
+ test_custom()
print("Done!")
except TestError as e:
werr(e.msg)
diff --git a/testfiles/custom/fidsErrMiss.cheby b/testfiles/custom/fidsErrMiss.cheby
new file mode 100644
index 0000000000000000000000000000000000000000..3a2a9161aeb155a160c92479074bfe75f2f9159d
--- /dev/null
+++ b/testfiles/custom/fidsErrMiss.cheby
@@ -0,0 +1,205 @@
+memory-map:
+ name: fidsErrMiss
+ bus: axi4-lite-32
+ size: 128
+ children:
+ - reg:
+ name: fidsCounters
+ description: event FIDS counters, see sub-registers for more info
+ width: 32
+ access: ro
+ address: 0x0
+ children:
+ - field:
+ name: missing
+ range: 7-0
+ - field:
+ name: erratic
+ range: 15-8
+ - field:
+ name: normal
+ range: 31-26
+ - reg:
+ name: pfnMeasOnEvent
+ description: PFN measurement on FIDS event (normal, missing or erratic)
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: refCalcPuComp1
+ description: dynamic calculated comparator1 PickUp DAC reference, based on Upfn
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: refCalcPuComp2
+ description: dynamic calculated comparator1 PickUp DAC reference, based on Upfn
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: pulseLengthTrigger
+ description: lenght of the trigger pulse
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: pulseLengthPuComp1
+ description: lenght of the pick-up pulse Comparator1
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: pulseLengthPuComp2
+ description: lenght of the pick-up pulse Comparator2
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: delayTrigComp1
+ description: assertion delay between trigger and comp1
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: delayTrigComp2
+ description: assertion delay between trigger and comp2
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: delayComp1Comp2
+ description: assertion delay between comp1 and comp2
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: puName
+ description: pick-up ASCII name
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: calcParamComp1
+ description: linear paramters for Upfn to ref comp1 conversion y=shift_right(x,s)*a+b
+ width: 32
+ access: rw
+ address: next
+ x_gena:
+ preset: 0xff01
+ children:
+ - field:
+ name: multiplier
+ description: signed integer
+ range: 7-0
+ preset: 0x1
+ - field:
+ name: offset
+ description: signed integer
+ range: 23-8
+ preset: 0xff
+ - field:
+ name: shiftRight
+ description: unsigned
+ range: 31-24
+ preset: 0x0
+ - reg:
+ name: calcParamComp2
+ description: linear paramters for Upfn to ref comp1 conversion y=shift_right(x,s)*a+b
+ width: 32
+ access: rw
+ address: next
+ x_gena:
+ preset: 0xff01
+ children:
+ - field:
+ name: multiplier
+ description: signed integer
+ range: 7-0
+ preset: 0x1
+ - field:
+ name: offset
+ description: signed integer
+ range: 23-8
+ preset: 0xff
+ - field:
+ name: shiftRight
+ description: unsigned
+ range: 31-24
+ preset: 0x0
+ - reg:
+ name: moduleParam
+ description: module bitwise parameters
+ width: 32
+ access: rw
+ address: next
+ x_gena:
+ preset: 0x0
+ children:
+ - field:
+ name: upfnAbs
+ description: on 1, use abs(upfn) for reference calculation
+ range: 0
+ preset: 0x0
+ - field:
+ name: resetCounters
+ description: on rising edge, reset FIDS counters to zero
+ range: 1
+ preset: 0x0
+ - reg:
+ name: windowLengthMissing
+ description: window missing length parameter
+ width: 32
+ access: rw
+ address: next
+ preset: 0x1f4
+ x_gena:
+ preset: 500
+ - reg:
+ name: windowLengthErratic
+ description: window erratic length parameter
+ width: 32
+ access: rw
+ address: next
+ preset: 0xfa
+ x_gena:
+ preset: 250
+ - reg:
+ name: maxCounterMissing
+ description: missing counter max. on which PLC interlock assertion
+ width: 32
+ access: rw
+ address: next
+ preset: 0x9
+ x_gena:
+ preset: 9
+ - reg:
+ name: maxCounterErratic
+ description: erratic counter max. on which PLC interlock assertion
+ width: 32
+ access: rw
+ address: next
+ preset: 0x9
+ x_gena:
+ preset: 9
+ - reg:
+ name: fallingDebounceLength
+ description: pickup falling edge debounce length
+ width: 32
+ access: rw
+ address: next
+ preset: 0x32
+ x_gena:
+ preset: 50
+ - reg:
+ name: refCalcPuComp1OnEvent
+ description: latched on event calculated comparator2 PickUp DAC reference, based on Upfn
+ width: 32
+ access: ro
+ address: next
+ - reg:
+ name: refCalcPuComp2OnEvent
+ description: latched on event calculated comparator2 PickUp DAC reference, based on Upfn
+ width: 32
+ access: ro
+ address: next
diff --git a/testfiles/custom/fidsErrMiss.h b/testfiles/custom/fidsErrMiss.h
new file mode 100644
index 0000000000000000000000000000000000000000..5de6b86a1f790a68fae1a959b4f74976214d2d36
--- /dev/null
+++ b/testfiles/custom/fidsErrMiss.h
@@ -0,0 +1,42 @@
+#ifndef FIDSERRMISS_FUNCTIONS_H_
+#define FIDSERRMISS_FUNCTIONS_H_
+
+//read functions ro data
+#define fidsErrMiss_read_ro \
+block->setfidsCounters(fasec->read_reg(0));\
+block->setpfnMeasOnEvent(fasec->read_reg(4));\
+block->setrefCalcPuComp1(fasec->read_reg(8));\
+block->setrefCalcPuComp2(fasec->read_reg(12));\
+block->setpulseLengthTrigger(fasec->read_reg(16));\
+block->setpulseLengthPuComp1(fasec->read_reg(20));\
+block->setpulseLengthPuComp2(fasec->read_reg(24));\
+block->setdelayTrigComp1(fasec->read_reg(28));\
+block->setdelayTrigComp2(fasec->read_reg(32));\
+block->setdelayComp1Comp2(fasec->read_reg(36));\
+block->setpuName(fasec->read_reg(40));\
+block->setrefCalcPuComp1OnEvent(fasec->read_reg(76));\
+block->setrefCalcPuComp2OnEvent(fasec->read_reg(80));\
+
+//read functions rw data
+#define fidsErrMiss_read_rw \
+block->setcalcParamComp1(fasec->read_reg(44));\
+block->setcalcParamComp2(fasec->read_reg(48));\
+block->setmoduleParam(fasec->read_reg(52));\
+block->setwindowLengthMissing(fasec->read_reg(56));\
+block->setwindowLengthErratic(fasec->read_reg(60));\
+block->setmaxCounterMissing(fasec->read_reg(64));\
+block->setmaxCounterErratic(fasec->read_reg(68));\
+block->setfallingDebounceLength(fasec->read_reg(72));\
+
+//write functions rw data
+#define fidsErrMiss_write_rw \
+fasec->write_reg(44,block->getcalcParamComp1());\
+fasec->write_reg(48,block->getcalcParamComp2());\
+fasec->write_reg(52,block->getmoduleParam());\
+fasec->write_reg(56,block->getwindowLengthMissing());\
+fasec->write_reg(60,block->getwindowLengthErratic());\
+fasec->write_reg(64,block->getmaxCounterMissing());\
+fasec->write_reg(68,block->getmaxCounterErratic());\
+fasec->write_reg(72,block->getfallingDebounceLength());\
+
+#endif