diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/CHANGES.txt b/circuit_board/wrs_v3/SCB_SAM9G45/CHANGES.txt index 0464e5fa329526f5796c1291e4ba3e7559b0c717..f062387573f1cbe53cebb59310d95360901dd373 100644 --- a/circuit_board/wrs_v3/SCB_SAM9G45/CHANGES.txt +++ b/circuit_board/wrs_v3/SCB_SAM9G45/CHANGES.txt @@ -1,3 +1,38 @@ +SCB Changes from V3.3 to V3.4: +=============================== + +Schematics: +------------ + + * C165 value changed from 100nF to 220nF + * VCC_IN of CDCM61002 (IC13) connected to +3V3 + * RSTN pin of IC13 conected to a 47nF capacitor, not to +3V3 + * QDRII_200CLK moved to OUT3 (LVPECL) of AD9516. + * Added LVDS termination resistor to adapt OUT3 to LVDS format + * CLK_OUT (EXTREF125MHZOUT) connected to OUT9 (CMOS) of AD9516-4. + * CLK_OUT transformer changed by 1:1 (WBC1-1LB) + * R253 and R254 resistor (Ethernet sheet) changed to 0402 size in order to reduce items. + * Changed EXTPPSIN input stage in order to add 50 R termination selectable by the FPGA. + * Name of nets QDRII_CLK and QDRII_200CLK changed to REF_CLK and AUX_CLK. + * Input EXTREF_125M removed. + * QDRII IC42 chip removed. + * Added ouput from FPGA latched by an AD9516 clock. This output uses the EXTREF_125M SMC connector: + * Added LVPECL latch + * Added LVPECL to LVTTL translator at the output + * CLK0 input of IC12 changed to OUT6 of AD9516 + * FPGA VCCO Bank 26 changed to +2V5 to use LVPECL and LVDS + * Removed the six 0R resistor at the inputs of the AD5662 DACs + * FPGA Banks 26, 36 and 25 moved to "PFGA_Peripherals_Control" sheet. + * Connected the 3 free buffers SN74LVT125DW to the EXTPPSOUT output signal. + +PCB: +------ + + * GTX_DIFF signals routed on 90um/160um in order to reduce space, allowing to pass between vias + * Some vias were moved from pads of some components to avoid the solder paste flooding by the vÃa. + * IVT3200 VCO was moved to separate it of NAND Flash IC + + Changes from SCBv3.2 to SCBv3.3 diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_100M_Ethernet.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_100M_Ethernet.SchDoc index c524125254840c1627056cb9ec7e22f0950b14fa..2744bd6e3ff66f1c73b268b2a293ad27f79774c8 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_100M_Ethernet.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_100M_Ethernet.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_DDR2.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_DDR2.SchDoc index 81ceb97f4220cdc072c96716e1c561d6279d4f2e..e4f490382574a818a5274680d51c048ddf28b2b2 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_DDR2.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_DDR2.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_EBI1_FPGA_Memory.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_EBI1_FPGA_Memory.SchDoc index 78ef00035ab701e5d9b852a32429c878c071594a..95aa28c09e32057d18898b87f7f7109f2d8be9b0 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_EBI1_FPGA_Memory.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_EBI1_FPGA_Memory.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_IO_Ports.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_IO_Ports.SchDoc index 59dfd9dca7e2ed0179ad5fcbe7b5167a6529b455..c3ede58b31c36fda2d9984c81c394577dc6661c7 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_IO_Ports.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_IO_Ports.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_JTAG_Power_PLL.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_JTAG_Power_PLL.SchDoc index 578800298907089ced89ccf714e3cde414ca7378..6def9d4cc7750125e3ae0812c2d3fce6610ac899 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/CPU_JTAG_Power_PLL.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/CPU_JTAG_Power_PLL.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/Connectors.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/Connectors.SchDoc index 2ba2cd72039a12c1e078a1702b524b9bb8f7aee2..2fb87a8b1aabe929c34103a68a0eec24459283bb 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/Connectors.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/Connectors.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/External WatchDogs.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/External WatchDogs.SchDoc index db6553c3e00cc5a58667935d34bee2417bf3a37a..6dc144363fd62ec42d7e78a82523f053786b9e73 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/External WatchDogs.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/External WatchDogs.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.Harness b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.Harness index db3f8b303650a271b2ce02c4189f980d611e70c8..f0bae66e0093a9cf2e4131a37c4acbde713750cc 100644 --- a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.Harness +++ b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.Harness @@ -1,3 +1,3 @@ FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM -QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N +PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.SchDoc index 216f5a9a99c8bae2d9d2c3da3828721117dc0882..4f4bebe5d2511bc7c7348923fdeff64ca2a2f3f6 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Configuration.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GPIOs.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GPIOs.SchDoc index 7c9b39c6d122ff7f41ebf55c62bfdf28e0173d53..4485299ac1413b916079ff5a2167b42fc83a21fb 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GPIOs.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GPIOs.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GTX.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GTX.SchDoc index 3a3eea2096f6ed74920a38000ed224791bd45e99..c610d39451eda98274774456428348a52d93e9e5 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GTX.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_GTX.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_POWER_DGND.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_POWER_DGND.SchDoc index 779d60da43ce62641be6309af90158b884355311..95fff69a997264f0ddc2ed53d1b5cc5833e3373c 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_POWER_DGND.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_POWER_DGND.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Peripherals_Control.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Peripherals_Control.SchDoc index 410d6d204c6d5e116f8e5e9bd0acf7f20e8d10c6..709f9b3119750ef5624149b9bc40dfa42201ac92 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Peripherals_Control.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_Peripherals_Control.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.Harness b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.Harness index 92285542724a31f97b54b61adbf3185230dea7d1..891e4731ee554e2cbd6b2a40622363108ae7d9e8 100644 --- a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.Harness +++ b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.Harness @@ -1,2 +1 @@ -qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\ qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.SchDoc index 443627b55b408d8a88a942ae7311d2d60411220d..7e85277d58c103058d91eb1ab43e1860f73e724c 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_QDRII.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_System_Monitor.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_System_Monitor.SchDoc index 236d61133aa2cc03a90300ef7d2ad4bf73b9a48b..422c3fe00c9b4f913699dea5f22a004afb881aaf 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_System_Monitor.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/FPGA_System_Monitor.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/Power_Supply.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/Power_Supply.SchDoc index 008e9e250a74510dbc9ea832722c60eb3bace839..bc5fcf7946c63b05d7c57b396b237d71cd4d0bee 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/Power_Supply.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/Power_Supply.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.Harness b/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.Harness index 92285542724a31f97b54b61adbf3185230dea7d1..891e4731ee554e2cbd6b2a40622363108ae7d9e8 100644 --- a/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.Harness +++ b/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.Harness @@ -1,2 +1 @@ -qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\ qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.SchDoc index a011eb07e4ae0aac9a9a47c9ba265a4a024056f0..bb101030b82a54760c50c80ccd1ddfd3f53275a2 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_mem.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_power.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_power.SchDoc index 5906a0397c93cb1ee720ef298461c2b3c91bd5bb..6697e402ab08771bb1fd3a25cd6b490c881a3c8c 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_power.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/QDRII_power.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/RS232_and_USB_ports.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/RS232_and_USB_ports.SchDoc index 9e400b42476dcb5fdb41b8e8ae729b82230bf980..f7ca287f74ec6832ee406a4e4058fc9b57751326 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/RS232_and_USB_ports.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/RS232_and_USB_ports.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCB b/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCB index 727329744a17fe494865c885db23679a0243db54..855511cde33a0b68e49287971ef9dd4ff129f81c 100644 --- a/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCB +++ b/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCB @@ -4,17 +4,22 @@ HierarchyMode=2 ChannelRoomNamingStyle=0 OutputPath=Project Outputs for SCB LogFolderPath= +ReleasesFolder= +ReleaseVaultGUID= +ReleaseVaultName= ChannelDesignatorFormatString=$Component_$RoomName ChannelRoomLevelSeperator=_ OpenOutputs=1 ArchiveProject=0 TimestampOutput=0 SeparateFolders=0 +TemplateLocationPath= PinSwapBy_Netlabel=1 PinSwapBy_Pin=0 AllowPortNetNames=0 AllowSheetEntryNetNames=1 AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 DefaultConfiguration= UserID=0xFFFFFFFF DefaultPcbProtel=1 @@ -23,6 +28,7 @@ ReorderDocumentsOnCompile=1 NameNetsHierarchically=0 PowerPortNamesTakePriority=0 PushECOToAnnotationFile=1 +DItemRevisionGUID= [Document1] DocumentPath=Power_Supply.SchDoc @@ -37,6 +43,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document2] DocumentPath=uTCA_MCH_PCB3.pcbdoc @@ -51,6 +59,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document3] DocumentPath=SCB_CLKs.SchDoc @@ -65,6 +75,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document4] DocumentPath=..\LIBS\footprints.PCBLIB @@ -79,6 +91,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document5] DocumentPath=..\LIBS\library.LIB @@ -93,6 +107,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document6] DocumentPath=..\LIBS\wr_switch.SCHLIB @@ -107,6 +123,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document7] DocumentPath=RS232_and_USB_ports.SchDoc @@ -121,6 +139,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document8] DocumentPath=CPU_EBI1_FPGA_Memory.SchDoc @@ -135,6 +155,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document9] DocumentPath=CPU_100M_Ethernet.SchDoc @@ -149,6 +171,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document10] DocumentPath=FPGA_GTX.SchDoc @@ -163,6 +187,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document11] DocumentPath=FPGA_Configuration.SchDoc @@ -177,6 +203,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document12] DocumentPath=CPU_IO_Ports.SchDoc @@ -191,6 +219,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document13] DocumentPath=External WatchDogs.SchDoc @@ -205,6 +235,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document14] DocumentPath=FPGA_POWER_DGND.SchDoc @@ -219,6 +251,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document15] DocumentPath=FPGA_QDRII.SchDoc @@ -233,6 +267,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document16] DocumentPath=CPU_JTAG_Power_PLL.SchDoc @@ -247,6 +283,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document17] DocumentPath=uTCA_Tongue3.SchDoc @@ -261,6 +299,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document18] DocumentPath=Connectors.SchDoc @@ -275,6 +315,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document19] DocumentPath=SCB_MAIN.SchDoc @@ -289,6 +331,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document20] DocumentPath=FPGA_GPIOs.SchDoc @@ -303,6 +347,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document21] DocumentPath=SCB_PLLs.SchDoc @@ -317,6 +363,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document22] DocumentPath=SMI_Link_7-12.SchDoc @@ -331,6 +379,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document23] DocumentPath=..\LIBS\QSS-048-01-X-D-DP-A.PcbLib @@ -345,6 +395,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document24] DocumentPath=..\LIBS\QSS-016-01-X-D-DP-A.PcbLib @@ -359,6 +411,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document25] DocumentPath=FPGA_System_Monitor.SchDoc @@ -373,51 +427,59 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document26] -DocumentPath=QDRII_mem.SchDoc +DocumentPath=..\LIBS\7S_WR.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 AnnotateSuffix= AnnotateScope=All -AnnotateOrder=24 +AnnotateOrder=-1 DoLibraryUpdate=1 DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=0 +ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document27] -DocumentPath=QDRII_power.SchDoc +DocumentPath=FPGA_Peripherals_Control.SchDoc AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 AnnotateSuffix= AnnotateScope=All -AnnotateOrder=25 +AnnotateOrder=27 DoLibraryUpdate=1 DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document28] -DocumentPath=QDRII_mem.Harness +DocumentPath=CPU_DDR2.SchDoc AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 AnnotateSuffix= AnnotateScope=All -AnnotateOrder=-1 +AnnotateOrder=28 DoLibraryUpdate=1 DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=1 +ClassGenCCAutoRoomEnabled=0 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document29] -DocumentPath=FPGA_Configuration.Harness +DocumentPath=..\..\..\..\..\Archivos de programa\Altium Designer Summer 09\Library\Xilinx\Xilinx Virtex-6.IntLib AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -429,9 +491,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document30] -DocumentPath=FPGA_GTX.Harness +DocumentPath=..\..\..\..\..\Archivos de programa\Altium Designer Summer 09\Library\Maxim\Maxim Footprints.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -443,9 +507,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document31] -DocumentPath=CPU_100M_Ethernet.Harness +DocumentPath=..\LIBS\QSE-020-01-X-D-A.PcbLib AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -457,9 +523,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document32] -DocumentPath=CPU_JTAG_Power_PLL.Harness +DocumentPath=Power_Supply.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -471,9 +539,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document33] -DocumentPath=CPU_IO_Ports.Harness +DocumentPath=SCB_CLKs.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -485,6 +555,8 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document34] DocumentPath=RS232_and_USB_ports.Harness @@ -499,9 +571,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document35] -DocumentPath=FPGA_QDRII.Harness +DocumentPath=CPU_100M_Ethernet.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -513,9 +587,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document36] -DocumentPath=Power_Supply.Harness +DocumentPath=FPGA_GTX.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -527,9 +603,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document37] -DocumentPath=Connectors.Harness +DocumentPath=FPGA_Configuration.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -541,9 +619,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document38] -DocumentPath=External WatchDogs.Harness +DocumentPath=CPU_IO_Ports.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -555,9 +635,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document39] -DocumentPath=..\LIBS\7S_WR.PcbLib +DocumentPath=External WatchDogs.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -569,23 +651,27 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document40] -DocumentPath=FPGA_Peripherals_Control.SchDoc +DocumentPath=FPGA_QDRII.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 AnnotateSuffix= AnnotateScope=All -AnnotateOrder=27 +AnnotateOrder=-1 DoLibraryUpdate=1 DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=0 +ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document41] -DocumentPath=SCB_PLLs.Harness +DocumentPath=CPU_JTAG_Power_PLL.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -597,9 +683,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document42] -DocumentPath=FPGA_Peripherals_Control.Harness +DocumentPath=Connectors.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -611,9 +699,11 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document43] -DocumentPath=SCB_CLKs.Harness +DocumentPath=SCB_PLLs.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 @@ -625,26 +715,231 @@ DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [Document44] -DocumentPath=CPU_DDR2.SchDoc +DocumentPath=FPGA_Peripherals_Control.Harness AnnotationEnabled=1 AnnotateStartValue=1 AnnotationIndexControlEnabled=0 AnnotateSuffix= AnnotateScope=All -AnnotateOrder=28 +AnnotateOrder=-1 DoLibraryUpdate=1 DoDatabaseUpdate=1 ClassGenCCAutoEnabled=1 -ClassGenCCAutoRoomEnabled=0 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 + +[Document45] +DocumentPath=..\..\..\..\..\Program Files\Altium Designer Summer 09\Library\ON Semiconductor\ON Semi Logic Flip-Flop.IntLib +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 + +[Document46] +DocumentPath=QDRII_mem.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 + +[Document47] +DocumentPath=QDRII_mem.Harness +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 +ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 + +[Document48] +DocumentPath=QDRII_power.SchDoc +AnnotationEnabled=1 +AnnotateStartValue=1 +AnnotationIndexControlEnabled=0 +AnnotateSuffix= +AnnotateScope=All +AnnotateOrder=-1 +DoLibraryUpdate=1 +DoDatabaseUpdate=1 +ClassGenCCAutoEnabled=1 +ClassGenCCAutoRoomEnabled=1 ClassGenNCAutoScope=None +DItemRevisionGUID= +GenerateClassCluster=0 [GeneratedDocument1] DocumentPath=Project Outputs for SCB\Design Rule Check - uTCA_MCH_PCB3.html +DItemRevisionGUID= [GeneratedDocument2] -DocumentPath=..\..\..\Documents and Settings\ciapek\Pulpit\SCB_SAM9G45\uTCA_MCH_PCB3.pcbdoc.htm +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3-RoundHoles-NonPlated.TXT +DItemRevisionGUID= + +[GeneratedDocument3] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3-RoundHoles-Plated.TXT +DItemRevisionGUID= + +[GeneratedDocument4] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3-SlotHoles-Plated.TXT +DItemRevisionGUID= + +[GeneratedDocument5] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.DRL +DItemRevisionGUID= + +[GeneratedDocument6] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.DRR +DItemRevisionGUID= + +[GeneratedDocument7] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.EXTREP +DItemRevisionGUID= + +[GeneratedDocument8] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.G1 +DItemRevisionGUID= + +[GeneratedDocument9] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.G2 +DItemRevisionGUID= + +[GeneratedDocument10] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.G3 +DItemRevisionGUID= + +[GeneratedDocument11] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.G4 +DItemRevisionGUID= + +[GeneratedDocument12] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GBL +DItemRevisionGUID= + +[GeneratedDocument13] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GBO +DItemRevisionGUID= + +[GeneratedDocument14] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GBP +DItemRevisionGUID= + +[GeneratedDocument15] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GBS +DItemRevisionGUID= + +[GeneratedDocument16] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GM1 +DItemRevisionGUID= + +[GeneratedDocument17] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GP1 +DItemRevisionGUID= + +[GeneratedDocument18] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GP2 +DItemRevisionGUID= + +[GeneratedDocument19] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GP3 +DItemRevisionGUID= + +[GeneratedDocument20] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GP4 +DItemRevisionGUID= + +[GeneratedDocument21] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GP5 +DItemRevisionGUID= + +[GeneratedDocument22] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GP6 +DItemRevisionGUID= + +[GeneratedDocument23] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GPB +DItemRevisionGUID= + +[GeneratedDocument24] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GPT +DItemRevisionGUID= + +[GeneratedDocument25] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GTL +DItemRevisionGUID= + +[GeneratedDocument26] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GTO +DItemRevisionGUID= + +[GeneratedDocument27] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GTP +DItemRevisionGUID= + +[GeneratedDocument28] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.GTS +DItemRevisionGUID= + +[GeneratedDocument29] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.LDP +DItemRevisionGUID= + +[GeneratedDocument30] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.REP +DItemRevisionGUID= + +[GeneratedDocument31] +DocumentPath=Project Outputs for SCB\uTCA_MCH_PCB3.RUL +DItemRevisionGUID= + +[Parameter1] +Name=Date +Value=12/06/2012 + +[Parameter2] +Name=Project +Value=White Rabbit + +[Parameter3] +Name=Revision +Value=3.2 + +[PCBConfiguration1] +ReleaseItemId= +CurrentRevision= +Name=Default Configuration +Variant=[No Variations] +GenerateBOM=0 [Generic_SmartPDF] AutoOpenFile=-1 @@ -680,124 +975,125 @@ SaveSettingsToOutJob=0 [OutputGroup1] Name=Netlist Outputs Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 -OutputType1=CadnetixNetlist -OutputName1=Cadnetix Netlist +OutputType1=WireListNetlist +OutputName1=WireList Netlist OutputDocumentPath1= OutputVariantName1= OutputDefault1=0 -OutputType2=CalayNetlist -OutputName2=Calay Netlist +OutputType2=CadnetixNetlist +OutputName2=Cadnetix Netlist OutputDocumentPath2= OutputVariantName2= OutputDefault2=0 -OutputType3=EDIF -OutputName3=EDIF for PCB +OutputType3=CalayNetlist +OutputName3=Calay Netlist OutputDocumentPath3= OutputVariantName3= OutputDefault3=0 -OutputType4=EESofNetlist -OutputName4=EESof Netlist +OutputType4=EDIF +OutputName4=EDIF for PCB OutputDocumentPath4= OutputVariantName4= OutputDefault4=0 -OutputType5=IntergraphNetlist -OutputName5=Intergraph Netlist +OutputType5=EESofNetlist +OutputName5=EESof Netlist OutputDocumentPath5= OutputVariantName5= OutputDefault5=0 -OutputType6=MentorBoardStationNetlist -OutputName6=Mentor BoardStation Netlist +OutputType6=IntergraphNetlist +OutputName6=Intergraph Netlist OutputDocumentPath6= OutputVariantName6= OutputDefault6=0 -OutputType7=MultiWire -OutputName7=MultiWire +OutputType7=MentorBoardStationNetlist +OutputName7=Mentor BoardStation Netlist OutputDocumentPath7= OutputVariantName7= OutputDefault7=0 -OutputType8=OrCadPCB2Netlist -OutputName8=Orcad/PCB2 Netlist +OutputType8=MultiWire +OutputName8=MultiWire OutputDocumentPath8= OutputVariantName8= OutputDefault8=0 -OutputType9=PADSNetlist -OutputName9=PADS ASCII Netlist +OutputType9=OrCadPCB2Netlist +OutputName9=Orcad/PCB2 Netlist OutputDocumentPath9= OutputVariantName9= OutputDefault9=0 -OutputType10=Pcad -OutputName10=Pcad for PCB +OutputType10=PADSNetlist +OutputName10=PADS ASCII Netlist OutputDocumentPath10= OutputVariantName10= OutputDefault10=0 -OutputType11=PCADNetlist -OutputName11=PCAD Netlist +OutputType11=Pcad +OutputName11=Pcad for PCB OutputDocumentPath11= OutputVariantName11= OutputDefault11=0 -OutputType12=PCADnltNetlist -OutputName12=PCADnlt Netlist +OutputType12=PCADNetlist +OutputName12=PCAD Netlist OutputDocumentPath12= OutputVariantName12= OutputDefault12=0 -OutputType13=Protel2Netlist -OutputName13=Protel2 Netlist +OutputType13=PCADnltNetlist +OutputName13=PCADnlt Netlist OutputDocumentPath13= OutputVariantName13= OutputDefault13=0 -OutputType14=ProtelNetlist -OutputName14=Protel +OutputType14=Protel2Netlist +OutputName14=Protel2 Netlist OutputDocumentPath14= OutputVariantName14= OutputDefault14=0 -OutputType15=RacalNetlist -OutputName15=Racal Netlist +OutputType15=ProtelNetlist +OutputName15=Protel OutputDocumentPath15= OutputVariantName15= OutputDefault15=0 -OutputType16=RINFNetlist -OutputName16=RINF Netlist +OutputType16=RacalNetlist +OutputName16=Racal Netlist OutputDocumentPath16= OutputVariantName16= OutputDefault16=0 -OutputType17=SciCardsNetlist -OutputName17=SciCards Netlist +OutputType17=RINFNetlist +OutputName17=RINF Netlist OutputDocumentPath17= OutputVariantName17= OutputDefault17=0 -OutputType18=SIMetrixNetlist -OutputName18=SIMetrix +OutputType18=SciCardsNetlist +OutputName18=SciCards Netlist OutputDocumentPath18= OutputVariantName18= OutputDefault18=0 -OutputType19=SIMPLISNetlist -OutputName19=SIMPLIS +OutputType19=SIMetrixNetlist +OutputName19=SIMetrix OutputDocumentPath19= OutputVariantName19= OutputDefault19=0 -OutputType20=TangoNetlist -OutputName20=Tango Netlist +OutputType20=SIMPLISNetlist +OutputName20=SIMPLIS OutputDocumentPath20= OutputVariantName20= OutputDefault20=0 -OutputType21=TelesisNetlist -OutputName21=Telesis Netlist +OutputType21=TangoNetlist +OutputName21=Tango Netlist OutputDocumentPath21= OutputVariantName21= OutputDefault21=0 -OutputType22=Verilog -OutputName22=Verilog File +OutputType22=TelesisNetlist +OutputName22=Telesis Netlist OutputDocumentPath22= OutputVariantName22= OutputDefault22=0 -OutputType23=VHDL -OutputName23=VHDL File +OutputType23=Verilog +OutputName23=Verilog File OutputDocumentPath23= OutputVariantName23= OutputDefault23=0 -OutputType24=WireListNetlist -OutputName24=WireList Netlist +OutputType24=VHDL +OutputName24=VHDL File OutputDocumentPath24= OutputVariantName24= OutputDefault24=0 @@ -810,6 +1106,7 @@ OutputDefault25=0 [OutputGroup2] Name=Simulator Outputs Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 OutputType1=AdvSimNetlist OutputName1=Mixed Sim @@ -830,134 +1127,184 @@ OutputDefault3=0 [OutputGroup3] Name=New Output Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 [OutputGroup4] Name=Assembly Outputs Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 OutputType1=Assembly OutputName1=Assembly Drawings OutputDocumentPath1= -OutputVariantName1= +OutputVariantName1=[No Variations] OutputDefault1=0 PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 OutputType2=Pick Place OutputName2=Generates pick and place files OutputDocumentPath2= -OutputVariantName2= +OutputVariantName2=[No Variations] OutputDefault2=0 +Configuration2_Name1=OutputConfigurationParameter1 +Configuration2_Item1=Record=PickPlaceView|Units=Metric|GenerateCSVFormat=True|GenerateTextFormat=True +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 [OutputGroup5] Name=Fabrication Outputs Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 -OutputType1=CompositeDrill -OutputName1=Composite Drill Drawing +OutputType1=NC Drill +OutputName1=NC Drill Files OutputDocumentPath1= OutputVariantName1= OutputDefault1=0 -PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +Configuration1_Name1=OutputConfigurationParameter1 +Configuration1_Item1=BoardEdgeRoutToolDia=2000000|GenerateBoardEdgeRout=False|GenerateDrilledSlotsG85=False|GenerateSeparatePlatedNonPlatedFiles=True|NumberOfDecimals=4|NumberOfUnits=4|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Record=DrillView|Units=Metric|ZeroesMode=SuppressTrailingZeroes OutputType2=Drill OutputName2=Drill Drawing/Guides OutputDocumentPath2= -OutputVariantName2= +OutputVariantName2=[No Variations] OutputDefault2=0 -PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 -OutputType3=Final -OutputName3=Final Artwork Prints +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=0.92|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +Configuration2_Name1=OutputConfigurationParameter1 +Configuration2_Item1=PrintArea=DesignExtent|PrintAreaLowerLeftCornerX=0|PrintAreaLowerLeftCornerY=0|PrintAreaUpperRightCornerX=0|PrintAreaUpperRightCornerY=0|Record=PcbPrintView +Configuration2_Name2=OutputConfigurationParameter2 +Configuration2_Item2=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=0|Mirror=False|Name=Drill Drawing For (Bottom Layer,Top Layer)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False +Configuration2_Name3=OutputConfigurationParameter3 +Configuration2_Item3=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=BottomLayer|DLayer2=TopLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=DrillDrawing|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name4=OutputConfigurationParameter4 +Configuration2_Item4=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name5=OutputConfigurationParameter5 +Configuration2_Item5=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical8|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name6=OutputConfigurationParameter6 +Configuration2_Item6=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical12|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name7=OutputConfigurationParameter7 +Configuration2_Item7=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name8=OutputConfigurationParameter8 +Configuration2_Item8=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name9=OutputConfigurationParameter9 +Configuration2_Item9=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=0|Record=PcbPrintLayer +Configuration2_Name10=OutputConfigurationParameter10 +Configuration2_Item10=IncludeBottomLayerComponents=True|IncludeMultiLayerComponents=True|IncludeTopLayerComponents=True|Index=1|Mirror=False|Name=Drill Guide For (Bottom Layer,Top Layer)|PadNumberFontSize=14|Record=PcbPrintOut|ShowHoles=False|ShowPadNets=False|ShowPadNumbers=False|SubstituteFonts=False +Configuration2_Name11=OutputConfigurationParameter11 +Configuration2_Item11=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=BottomLayer|DLayer2=TopLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=DrillGuide|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +Configuration2_Name12=OutputConfigurationParameter12 +Configuration2_Item12=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical1|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +Configuration2_Name13=OutputConfigurationParameter13 +Configuration2_Item13=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical8|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +Configuration2_Name14=OutputConfigurationParameter14 +Configuration2_Item14=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical12|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +Configuration2_Name15=OutputConfigurationParameter15 +Configuration2_Item15=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical13|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +Configuration2_Name16=OutputConfigurationParameter16 +Configuration2_Item16=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical14|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +Configuration2_Name17=OutputConfigurationParameter17 +Configuration2_Item17=CArc=Full|CFill=Full|Comment=Full|Coordinate=Full|CPad=Full|CRegion=Full|CText=Full|CTrack=Full|CVia=Full|DDSymbolKind=0|DDSymbolSize=500000|DDSymbolSortKind=0|Designator=Full|Dimension=Full|DLayer1=TopLayer|DLayer2=BottomLayer|FArc=Full|FFill=Full|FPad=Full|FRegion=Full|FText=Full|FTrack=Full|FVia=Full|Layer=Mechanical15|Polygon=Full|PrintOutIndex=1|Record=PcbPrintLayer +OutputType3=CompositeDrill +OutputName3=Composite Drill Drawing OutputDocumentPath3= -OutputVariantName3= +OutputVariantName3=[No Variations] OutputDefault3=0 PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 -OutputType4=Gerber -OutputName4=Gerber Files +OutputType4=Final +OutputName4=Final Artwork Prints OutputDocumentPath4= -OutputVariantName4= +OutputVariantName4=[No Variations] OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 OutputType5=Mask OutputName5=Solder/Paste Mask Prints OutputDocumentPath5= OutputVariantName5= OutputDefault5=0 PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 -OutputType6=NC Drill -OutputName6=NC Drill Files +OutputType6=Plane +OutputName6=Power-Plane Prints OutputDocumentPath6= OutputVariantName6= OutputDefault6=0 +PageOptions6=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 OutputType7=ODB OutputName7=ODB++ Files OutputDocumentPath7= -OutputVariantName7= +OutputVariantName7=[No Variations] OutputDefault7=0 -OutputType8=Plane -OutputName8=Power-Plane Prints +OutputType8=Test Points +OutputName8=Test Point Report OutputDocumentPath8= OutputVariantName8= OutputDefault8=0 -PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 -OutputType9=Test Points -OutputName9=Test Point Report +OutputType9=Gerber +OutputName9=Gerber Files OutputDocumentPath9= -OutputVariantName9= +OutputVariantName9=[No Variations] OutputDefault9=0 +Configuration9_Name1=OutputConfigurationParameter1 +Configuration9_Item1=AddToAllPlots.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|CentrePlots=False|DrillDrawingSymbol=GraphicsSymbol|DrillDrawingSymbolSize=500000|EmbeddedApertures=True|FilmBorderSize=10000000|FilmXSize=200000000|FilmYSize=160000000|FlashAllFills=False|FlashPadShapes=True|G54OnApertureChange=False|GenerateDRCRulesFile=True|GenerateReliefShapes=True|GerberUnit=Metric|IncludeUnconnectedMidLayerPads=False|LeadingAndTrailingZeroesMode=SuppressLeadingZeroes|MaxApertureSize=2500000|MinusApertureTolerance=39|Mirror.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean|MirrorDrillDrawingPlots=False|MirrorDrillGuidePlots=False|NumberOfDecimals=4|OptimizeChangeLocationCommands=True|OriginPosition=Relative|Panelize=False|Plot.Set=SerializeLayerHash.Version~2,ClassName~TLayerToBoolean,16973830~1,16973832~1,16973834~1,16777217~1,16842753~1,16777218~1,16842754~1,16777220~1,16842755~1,16842756~1,16777221~1,16842757~1,16777219~1,16842758~1,16842751~1,16973835~1,16973833~1,16973831~1,16908289~1,16973848~1,16973849~1|PlotPositivePlaneLayers=False|PlotUsedDrillDrawingLayerPairs=False|PlotUsedDrillGuideLayerPairs=False|PlusApertureTolerance=39|Record=GerberView|SoftwareArcs=False|Sorted=False [OutputGroup6] Name=Report Outputs Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 -OutputType1=Script -OutputName1=Script Output +OutputType1=SinglePinNetReporter +OutputName1=Report Single Pin Nets OutputDocumentPath1= -OutputVariantName1= +OutputVariantName1=[No Variations] OutputDefault1=0 -OutputType2=SimpleBOM -OutputName2=Simple BOM +Configuration1_Name1=OutputConfigurationParameter1 +Configuration1_Item1=NetlistVersion=0|Record=SinglePinNetsView +OutputType2=BOM_PartType +OutputName2=Bill of Materials OutputDocumentPath2= -OutputVariantName2= +OutputVariantName2=[No Variations] OutputDefault2=0 -OutputType3=SinglePinNetReporter -OutputName3=Report Single Pin Nets +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +Configuration2_Name1=Filter +Configuration2_Item1=545046300E5446696C74657257726170706572000D46696C7465722E416374697665090F46696C7465722E43726974657269610A04000000000000000000 +Configuration2_Name2=General +Configuration2_Item2=OpenExported=False|AddToProject=False|ForceFit=False|NotFitted=False|Database=False|IncludePCBData=True|ShowExportOptions=True|TemplateFilename=|BatchMode=0|FormWidth=1890|FormHeight=990|SupplierProdQty=1|SupplierAutoQty=False|SupplierUseCachedPricing=False|SupplierCurrency=<none> +Configuration2_Name3=GroupOrder +Configuration2_Item3=Designator=True|Mounted=True|Comment=True|Footprint=True +Configuration2_Name4=OutputConfigurationParameter1 +Configuration2_Item4=Record=BOMPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False +Configuration2_Name5=PCBDocument +Configuration2_Item5=FileName=uTCA_MCH_PCB3.pcbdoc +Configuration2_Name6=SortOrder +Configuration2_Item6=SheetNumber=Up +Configuration2_Name7=VisibleOrder +Configuration2_Item7=Mounted=57|Designator=70|Center-X(mm)=86|Center-Y(mm)=86|Pad-X(mm)=86|Pad-Y(mm)=86|Ref-X(mm)=86|Ref-Y(mm)=86|Layer=86|Rotation=81|Manufacturer1 PN=53|Manufacturer1=53|Comment=79|Description=112|Distributor1=61|Distributor1 PN=67|SheetNumber=71 +OutputType3=ComponentCrossReference +OutputName3=Component Cross Reference Report OutputDocumentPath3= -OutputVariantName3= +OutputVariantName3=[No Variations] OutputDefault3=0 -Configuration3_Name1=OutputConfigurationParameter1 -Configuration3_Item1=NetlistVersion=0|Record=SinglePinNetsView -OutputType4=BOM_PartType -OutputName4=Bill of Materials +OutputType4=ReportHierarchy +OutputName4=Report Project Hierarchy OutputDocumentPath4= -OutputVariantName4= +OutputVariantName4=[No Variations] OutputDefault4=0 -PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 -Configuration4_Name1=OutputConfigurationParameter1 -Configuration4_Item1=Record=BOMPrintView|ShowNoERC=True|ShowParamSet=True|ShowProbe=True|ShowBlanket=True|ExpandDesignator=True|ExpandNetLabel=False|ExpandPort=False|ExpandSheetNum=False|ExpandDocNum=False -OutputType5=ComponentCrossReference -OutputName5=Component Cross Reference Report +OutputType5=Script +OutputName5=Script Output OutputDocumentPath5= -OutputVariantName5= +OutputVariantName5=[No Variations] OutputDefault5=0 -OutputType6=ReportHierarchy -OutputName6=Report Project Hierarchy +OutputType6=SimpleBOM +OutputName6=Simple BOM OutputDocumentPath6= -OutputVariantName6= +OutputVariantName6=[No Variations] OutputDefault6=0 -OutputType7=Design Rules Check -OutputName7=Design Rules Check -OutputDocumentPath7= -OutputVariantName7= -OutputDefault7=0 -PageOptions7=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=Letter|PrintScaleMode=1 -OutputType8=Electrical Rules Check -OutputName8=Electrical Rules Check -OutputDocumentPath8= -OutputVariantName8= -OutputDefault8=0 -PageOptions8=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=Letter|PrintScaleMode=1 [OutputGroup7] Name=Other Outputs Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 OutputType1=Text Print OutputName1=Text Print @@ -1121,6 +1468,58 @@ OutputDocumentPath27= OutputVariantName27= OutputDefault27=0 PageOptions27=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +OutputType28=Text Print +OutputName28=Text Print +OutputDocumentPath28= +OutputVariantName28= +OutputDefault28=0 +PageOptions28=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +OutputType29=Text Print +OutputName29=Text Print +OutputDocumentPath29= +OutputVariantName29= +OutputDefault29=0 +PageOptions29=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 + +[OutputGroup8] +Name=Validation Outputs +Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 +OutputType1=Electrical Rules Check +OutputName1=Electrical Rules Check +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=Letter|PrintScaleMode=1 +OutputType2=Design Rules Check +OutputName2=Design Rules Check +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +OutputType3=Differences Report +OutputName3=Differences Report +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 +OutputType4=Footprint Comparison Report +OutputName4=Footprint Comparison Report +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 + +[OutputGroup9] +Name=Export Outputs +Description= +TargetPrinter=Kyocera FS-C2126MFP+ KX +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1 +OutputType1=ExportSTEP +OutputName1=Export STEP +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 [Modification Levels] Type1=1 @@ -1189,6 +1588,14 @@ Type63=1 Type64=1 Type65=1 Type66=1 +Type67=1 +Type68=1 +Type69=1 +Type70=1 +Type71=1 +Type72=1 +Type73=1 +Type74=1 [Difference Levels] Type1=1 @@ -1225,9 +1632,15 @@ Type31=1 Type32=1 Type33=1 Type34=1 +Type35=1 +Type36=1 +Type37=1 +Type38=1 +Type39=1 +Type40=1 [Electrical Rules Check] -Type1=1 +Type1=0 Type2=1 Type3=2 Type4=1 @@ -1240,7 +1653,7 @@ Type10=1 Type11=2 Type12=2 Type13=2 -Type14=1 +Type14=0 Type15=1 Type16=1 Type17=1 @@ -1325,6 +1738,8 @@ Type95=2 Type96=2 Type97=2 Type98=0 +Type99=1 +Type100=2 [ERC Connection Matrix] L1=NNNNNNNNNNNWNNNWW @@ -1368,6 +1783,7 @@ PartTypes=0 FullReplace=1 UpdateDesignatorLock=1 UpdatePartIDLock=1 +PreserveParameterLocations=1 DoGraphics=1 DoParameters=1 DoModels=1 @@ -1387,6 +1803,7 @@ ComparisonOptions1=Kind=Net Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm= ComparisonOptions2=Kind=Component Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 ComparisonOptions3=Kind=Rule|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 ComparisonOptions4=Kind=Differential Pair|MinPercent=50|MinMatch=1|ShowMatch=0|Confirm=0|UseName=0|InclAllRules=0 +ComparisonOptions5=Kind=Structure Class|MinPercent=75|MinMatch=3|ShowMatch=-1|Confirm=-1|UseName=-1|InclAllRules=0 [SmartPDF] PageOptions=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1 diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCBStructure b/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCBStructure new file mode 100644 index 0000000000000000000000000000000000000000..736c318f7ce1a14524048ce47b36fe19299c870a --- /dev/null +++ b/circuit_board/wrs_v3/SCB_SAM9G45/SCB.PrjPCBStructure @@ -0,0 +1,24 @@ +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_Connectors|SchDesignator=U_Connectors|FileName=Connectors.SchDoc|SymbolType=Normal|RawFileName=Connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_100M_Ethernet|SchDesignator=U_CPU_100M_Ethernet|FileName=CPU_100M_Ethernet.SchDoc|SymbolType=Normal|RawFileName=CPU_100M_Ethernet.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_DDR2|SchDesignator=U_CPU_DDR2|FileName=CPU_DDR2.SchDoc|SymbolType=Normal|RawFileName=CPU_DDR2.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_EBI1_FPGA_Memory|SchDesignator=U_CPU_EBI1_FPGA_Memory|FileName=CPU_EBI1_FPGA_Memory.SchDoc|SymbolType=Normal|RawFileName=CPU_EBI1_FPGA_Memory.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_IO_Ports|SchDesignator=U_CPU_IO_Ports|FileName=CPU_IO_Ports.SchDoc|SymbolType=Normal|RawFileName=CPU_IO_Ports.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_JTAG_Power_PLL|SchDesignator=U_CPU_JTAG_Power_PLL|FileName=CPU_JTAG_Power_PLL.SchDoc|SymbolType=Normal|RawFileName=CPU_JTAG_Power_PLL.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_External WatchDogs|SchDesignator=U_External WatchDogs|FileName=External WatchDogs.SchDoc|SymbolType=Normal|RawFileName=External WatchDogs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_Configuration|SchDesignator=U_FPGA_Configuration|FileName=FPGA_Configuration.SchDoc|SymbolType=Normal|RawFileName=FPGA_Configuration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_GPIOs|SchDesignator=U_FPGA_GPIOs|FileName=FPGA_GPIOs.SchDoc|SymbolType=Normal|RawFileName=FPGA_GPIOs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_GTX|SchDesignator=U_FPGA_GTX|FileName=FPGA_GTX.SchDoc|SymbolType=Normal|RawFileName=FPGA_GTX.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_POWER_DGND|SchDesignator=U_FPGA_POWER_DGND|FileName=FPGA_POWER_DGND.SchDoc|SymbolType=Normal|RawFileName=FPGA_POWER_DGND.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_QDRII|SchDesignator=U_FPGA_QDRII|FileName=FPGA_QDRII.SchDoc|SymbolType=Normal|RawFileName=FPGA_QDRII.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_System_Monitor|SchDesignator=U_FPGA_System_Monitor|FileName=FPGA_System_Monitor.SchDoc|SymbolType=Normal|RawFileName=FPGA_System_Monitor.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= +Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_Peripherals_Control|SchDesignator=U_Peripherals_Control|FileName=FPGA_Peripherals_Control.SchDoc|SymbolType=Normal|RawFileName=FPGA_Peripherals_Control.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol|RevisionGUID= |ItemGUID= |VaultGUID= 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diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_CLKs.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_CLKs.SchDoc index 36d7703a0febda87d8223ce6064ac315d9758ad5..ed53c3bbfe1c877301a473534e272deae9d68ac4 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_CLKs.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_CLKs.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_MAIN.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_MAIN.SchDoc index 3737584e1248cb7cc316738157fae6f8eecd0c00..5d7e1cf711f5d3c845ca08d2025cf9a0bed8992a 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_MAIN.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_MAIN.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.Harness b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.Harness index 27e15f18827246c3e189b41d5258178ac6be2de8..9389ef6ee48b6391df7d8f53d8e60c4c3d112fce 100644 --- a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.Harness +++ b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.Harness @@ -1,4 +1,4 @@ MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N +PLL_CLKS=REF_CLK_P,REF_CLK_N,AUX_CLK_P,AUX_CLK_N PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS,CLK1_SEL,CLK_EN -QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N,MINIBACKPLANE_CLK_P,MINIBACKPLANE_CLK_N diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.SchDoc index 2a55d94ee228bc6cc4b66445d6250e7bd9aade92..5658e7b4693c83ee2a0ef4f371789e51f6efda06 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/SCB_PLLs.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/SMI_Link_7-12.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/SMI_Link_7-12.SchDoc index 5686173f86fa24b18d5730593a14abf63a53a42a..caf6feef07fef7e682a62e0e85eed1cfe074a9bf 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/SMI_Link_7-12.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/SMI_Link_7-12.SchDoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_MCH_PCB3.pcbdoc b/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_MCH_PCB3.pcbdoc index e2ed839b09208358ea3e29ad3bfb36d005633f26..41cd58dff6bdd639c3257447d537532c7a51d278 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_MCH_PCB3.pcbdoc and b/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_MCH_PCB3.pcbdoc differ diff --git a/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_Tongue3.SchDoc b/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_Tongue3.SchDoc index b89d8e0398b27fdcbfa933de942acfe13d60acae..35567526c835029036a09b8075016183442e96aa 100644 Binary files a/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_Tongue3.SchDoc and b/circuit_board/wrs_v3/SCB_SAM9G45/uTCA_Tongue3.SchDoc differ