wrapper.vhd 5.65 KB
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----------------------------------------------------------------------------------------------------------------------
-- Title      : wrapper
-- Project    : MUCTPI

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-- File       : wrapper.vhd
-- Author     : Marcos Oliveira
-- Company    : CERN
-- Created    : 2018-12-05
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-- Last update: 2018-12-12
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-- Platform   : Vivado 2017.2 and Mentor Modelsim SE-64 10.4a
-- Standard   : VHDL'93/02
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-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
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-- Revisions  :
-- Date        Version  Author  Description
-- 2018-12-05  1.0      msilvaol        Created
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library ieee;
use ieee.std_logic_1164.all;
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use IEEE.math_real.all;

use work.MuctpiDataTypes.all;
use work.MuctpiFunctions.all;
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entity wrapper is

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	generic(
		I     : natural  := 16;
		O     : natural  := 16;
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		delay : natural := 3           -- delay in clock cycles for pipeline register
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	);

	port(
		clk_wrapper : in  std_logic;
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		clk    : in  std_logic;
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		input       : in  std_logic;
		output      : out std_logic);
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		attribute syn_loc : string;
		attribute syn_pad_type : string;				
		attribute syn_loc of clk_wrapper :signal is"AU33"; 
		attribute syn_loc of clk :signal is"AV33";
		attribute syn_loc of input :signal is"AN32";
		attribute syn_loc of output :signal is"AU31";
		attribute syn_pad_type of clk_wrapper : signal is "LVCMOS18";						
		attribute syn_pad_type of clk : signal is "LVCMOS18";						
		attribute syn_pad_type of input : signal is "LVCMOS18";						
		attribute syn_pad_type of output  : signal is "LVCMOS18";						
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end entity wrapper;

architecture rtl of wrapper is

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  --constants
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  constant i_width         : integer := I*MuonCandidateLength;
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  constant o_width_desired : integer := O*MuonCandidateLength;
  constant log4_o_width    : integer := integer(ceil(log(real(o_width_desired), real(4))));
  constant o_width         : integer := 4**log4_o_width;

  --components

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  component lfsr is
    generic (
      WIDTH : natural);
    port (
      clock         : in  std_logic;
      input_bit     : in  std_logic;
      output_vector : out std_logic_vector(WIDTH-1 downto 0));
  end component lfsr;

  component reducer is
    generic (
      input_width_log4 : natural);
    port (
      clock        : in  std_logic;
      input_vector : in  std_logic_vector(4**input_width_log4-1 downto 0);
      output_bit   : out std_logic);
  end component reducer;

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  signal input_vector  : std_logic_vector(i_width-1 downto 0) := (others => '0');
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  signal input_slr     : std_logic_vector(i_width-1 downto 0) := (others => '0');
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  signal output_vector : std_logic_vector(o_width-1 downto 0) := (others => '0');
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  signal output_slr    : std_logic_vector(o_width-1 downto 0) := (others => '0');
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  signal muon_cand    : MuonCandidateArray(0 to I-1);
  signal muon_cand_c  : MuonCandidateArray(0 to I-1);
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  signal top_cand     : MuonCandidateArray(0 to O-1);
  signal source_valid : std_logic;
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  attribute DONT_TOUCH                  : string;
  attribute DONT_TOUCH of lsfr_1        : label is "TRUE";
  attribute DONT_TOUCH of reducer_1     : label is "TRUE";
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  --attribute DONT_TOUCH of muon_sorter_1 : label is "TRUE";
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--  attribute KEEP              : string;
--  attribute KEEP of muon_cand : signal is "TRUE";
--  attribute KEEP of top_cand : signal is "TRUE";
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begin                                   -- architecture rtl
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  lsfr_1 : lfsr
    generic map (
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      WIDTH => i_width)
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    port map (
      clock         => clk_wrapper,
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      input_bit     => input,
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      output_vector => input_vector);
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        shift_reg_tap_i : entity work.shift_reg_tap
    generic map (
      dw => i_width,
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      tw => 2)
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    port map (
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      clk    => clk,
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      ce     => '1',
      tap    => (others => '1'),
      input  => input_vector,
      output => input_slr);
      
        shift_reg_tap_o : entity work.shift_reg_tap
    generic map (
      dw => o_width,
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      tw => 2)
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    port map (
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      clk    => clk,
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      ce     => '1',
      tap    => (others => '1'),
      input  => output_vector,
      output => output_slr);

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  reducer_1 : reducer
    generic map (
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      input_width_log4 => log4_o_width)
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    port map (
      clock        => clk_wrapper,
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      input_vector => output_slr,
      output_bit   => output);
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  ----------------------------------------------------------------------------------------------------------------------
  -- Logic being tested
  ----------------------------------------------------------------------------------------------------------------------

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  process (clk) is
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  begin
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    if rising_edge(clk) then
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      muon_cand <= muon_cand_c;
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    end if;
  end process;

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  muon_cand_c                                     <= to_array(input_slr, I);
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  output_vector(O*MuonCandidateLength-1 downto 0) <= to_stdv(top_cand, O);

  muon_sorter_1 : entity work.muon_sorter
    generic map (
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      num_in  => I,
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      num_out => O,
      delay => delay)
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    port map (
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      clk          => clk,
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      sink_valid   => '1',
      source_valid => source_valid,
      muon_cand    => muon_cand,
      top_cand     => top_cand);

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end architecture rtl;