Commit 0fe46fb6 authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
Browse files

all the files 16x2

parent 161e5229
Implementation,LUTs,FFs,Logic Levels,LL-1,LL+1,High Fanout,HF-1,HF+1,Routes,Routes-1,Routes+1,Requirement,Req-1,Req+1,Path Delay,PD-1,PD+1,Slack,Slack-1,Slack+1,Logic Delay,LD-1,LD+1,Net Delay,ND-1,ND+1
../syn/prj_I016_O016_D000,5911,0,47,0,0,42,4,1,47,1,1,6.250,6.250,6.250,19.215,1.435,0.482,-12.884,4.646,5.411,5.319(28%),0.094(7%),0.096(20%),13.896(72%),1.341(93%),0.386(80%)
../syn/prj_I016_O016_D001,5870,607,26,0,26,25,3,44,26,1,26,6.250,6.250,6.250,10.249,1.789,9.477,-4.143,4.331,-3.432,3.004(30%),0.095(6%),3.077(33%),7.245(70%),1.694(94%),6.400(67%)
../syn/prj_I016_O016_D002,5674,1303,26,0,23,16,3,51,26,1,23,6.250,6.250,6.250,10.063,0.750,9.513,-3.882,5.431,-3.331,2.696(27%),0.098(14%),2.916(31%),7.367(73%),0.652(86%),6.597(69%)
../syn/prj_I016_O016_D003,5711,1203,24,0,0,19,3,1,24,1,1,6.250,6.250,6.250,9.548,1.100,0.781,-3.169,5.008,5.187,2.872(31%),0.096(9%),0.095(13%),6.676(69%),1.004(91%),0.686(87%)
../syn/prj_I016_O016_D004,5908,987,26,0,21,53,3,47,26,1,22,6.250,6.250,6.250,10.765,1.947,9.340,-4.665,4.203,-3.237,3.211(30%),0.096(5%),2.778(30%),7.554(70%),1.851(95%),6.562(70%)
../syn/prj_I016_O016_D005,5825,906,25,19,3,44,43,16,25,19,4,6.250,6.250,6.250,9.813,8.581,3.649,-3.621,-2.386,2.442,2.776(29%),2.645(31%),0.539(15%),7.037(71%),5.936(69%),3.110(85%)
../syn/prj_I032_O016_D000,19907,0,74,0,0,59,4,1,74,1,1,6.250,6.250,6.250,32.070,1.103,0.367,-25.754,5.015,5.581,8.678(28%),0.094(9%),0.096(27%),23.392(72%),1.009(91%),0.271(73%)
../syn/prj_I032_O016_D001,19411,2119,37,30,0,58,51,1,37,30,1,6.250,6.250,6.250,19.520,16.408,0.562,-13.434,-10.276,5.598,4.503(24%),2.837(18%),0.093(17%),15.017(76%),13.571(82%),0.469(83%)
../syn/prj_I032_O016_D002,19712,3088,36,0,28,49,4,51,37,1,28,6.250,6.250,6.250,19.063,0.749,16.437,-12.653,5.374,-10.606,4.046(22%),0.099(14%),3.617(23%),15.017(78%),0.650(86%),12.820(77%)
../syn/prj_I032_O016_D003,19942,3039,35,0,36,62,4,56,35,1,36,6.250,6.250,6.250,18.081,1.880,17.145,-12.055,4.234,-11.024,3.835(22%),0.098(6%),3.959(24%),14.246(78%),1.782(94%),13.186(76%)
../syn/prj_I032_O016_D004,19842,2812,33,0,35,59,4,58,33,1,35,6.250,6.250,6.250,16.655,1.384,15.876,-10.540,4.737,-9.709,3.810(23%),0.097(8%),3.925(25%),12.845(77%),1.287(92%),11.951(75%)
../syn/prj_I032_O016_D005,20443,3007,37,0,38,53,2,52,37,1,39,6.250,6.250,6.250,19.390,2.155,16.860,-13.072,3.962,-11.033,4.523(24%),0.097(5%),4.578(28%),14.867(76%),2.058(95%),12.282(72%)
../syn/prj_I032_O016_D006,19874,2521,33,0,2,59,4,1,33,1,3,6.250,6.250,6.250,16.866,1.124,1.833,-10.752,5.021,4.309,3.772(23%),0.096(9%),0.361(20%),13.094(77%),1.028(91%),1.472(80%)
../syn/prj_I032_O016_D007,20167,2685,34,0,1,46,3,1,34,1,2,6.250,6.250,6.250,17.016,0.549,1.997,-10.796,5.582,3.947,4.377(26%),0.096(18%),0.269(14%),12.639(74%),0.453(82%),1.728(86%)
Implementation,LUTs,FFs,Logic Levels,LL-1,LL+1,High Fanout,HF-1,HF+1,Routes,Routes-1,Routes+1,Requirement,Req-1,Req+1,Path Delay,PD-1,PD+1,Slack,Slack-1,Slack+1,Logic Delay,LD-1,LD+1,Net Delay,ND-1,ND+1
......@@ -37,9 +37,19 @@ entity wrapper is
port(
clk_wrapper : in std_logic;
clk_user : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
attribute syn_loc : string;
attribute syn_pad_type : string;
attribute syn_loc of clk_wrapper :signal is"AU33";
attribute syn_loc of clk :signal is"AV33";
attribute syn_loc of input :signal is"AN32";
attribute syn_loc of output :signal is"AU31";
attribute syn_pad_type of clk_wrapper : signal is "LVCMOS18";
attribute syn_pad_type of clk : signal is "LVCMOS18";
attribute syn_pad_type of input : signal is "LVCMOS18";
attribute syn_pad_type of output : signal is "LVCMOS18";
end entity wrapper;
......@@ -108,7 +118,7 @@ begin -- architecture rtl
dw => i_width,
tw => 4)
port map (
clk => clk_user,
clk => clk,
ce => '1',
tap => (others => '1'),
input => input_vector,
......@@ -119,7 +129,7 @@ begin -- architecture rtl
dw => o_width,
tw => 4)
port map (
clk => clk_user,
clk => clk,
ce => '1',
tap => (others => '1'),
input => output_vector,
......@@ -139,9 +149,9 @@ begin -- architecture rtl
-- Logic being tested
----------------------------------------------------------------------------------------------------------------------
process (clk_user) is
process (clk) is
begin
if rising_edge(clk_user) then
if rising_edge(clk) then
muon_cand <= muon_cand_c;
end if;
end process;
......@@ -155,7 +165,7 @@ begin -- architecture rtl
num_out => O,
delay => delay)
port map (
clk => clk_user,
clk => clk,
sink_valid => '1',
source_valid => source_valid,
muon_cand => muon_cand,
......
proc create_run {I O D {run 0}} {
puts "Creating run with I = $I, O = $O, D = $D"
set prjname [format "prj_I%03d_O%03d_D%03d" $I $O $D]
set basepath "D:/mygitlab/sorting"
set prjpath [format "%s/syn/%s/wrapper_%s.prj" $basepath $prjname $prjname]
set subprjpath [format "%s/syn/%s/muon_sorter_1/muon_sorter_%s.prj" $basepath $prjname $prjname]
puts $prjpath
puts $subprjpath
project -new $prjpath
add_file -vhdl ${basepath}/src/rtl/MuctpiDataTypes.vhd
add_file -vhdl ${basepath}/src/rtl/MuctpiFunctions.vhd
add_file -verilog ${basepath}/src/rtl/lfsr.sv
add_file -vhdl ${basepath}/src/rtl/muon_sorter.vhd
add_file -verilog ${basepath}/src/rtl/reducer.sv
add_file -vhdl ${basepath}/src/rtl/shift_reg_tap.vhd
add_file -vhdl ${basepath}/src/rtl/wrapper.vhd
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
set_option -disable_io_insertion 0
set_option -part XCVU9P
set_option -package FLGC2104
set_option -vhdl2008 1
set_option -retiming 0
set_option -frequency 160
set_option -fanout_limit 16
hdl_param -set I $I
hdl_param -set O $O
hdl_param -set delay $D
project -save $prjpath
project -run compile
cd ${basepath}/syn
export_project -instance muon_sorter_1 -add_file {../src/rtl/MuctpiDataTypes.vhd ../src/rtl/MuctpiFunctions.vhd ../src/rtl/muon_sorter.vhd} -no_default_hdl -project $subprjpath
project_data -active $subprjpath
proc create_run {I O D {run 1} opt} {
puts "Creating run with I = $I, O = $O, D = $D"
set prjpre [format "I%03d_O%03d_D%03d" $I $O $D]
set prjname [format "%s-%s" $prjpre $opt]
set basepath "D:/mygitlab/sorting"
set prjpath [format "%s/syn/%s/wrapper_%s.prj" $basepath $prjname $prjname]
set subprjpath [format "%s/syn/%s/muon_sorter_1/muon_sorter_%s.prj" $basepath $prjname $prjname]
puts $prjpath
puts $subprjpath
project -new $prjpath
add_file -vhdl ${basepath}/src/rtl/MuctpiDataTypes.vhd
add_file -vhdl ${basepath}/src/rtl/MuctpiFunctions.vhd
add_file -verilog ${basepath}/src/rtl/lfsr.sv
add_file -vhdl ${basepath}/src/rtl/muon_sorter.vhd
add_file -verilog ${basepath}/src/rtl/reducer.sv
add_file -vhdl ${basepath}/src/rtl/shift_reg_tap.vhd
add_file -vhdl ${basepath}/src/rtl/wrapper.vhd
set_option -disable_io_insertion 0
set_option -part XCVU9P
set_option -package FLGC2104
set_option -vhdl2008 1
set_option -retiming 0
switch $opt {
freq160retfan10000 {
set_option -frequency 160
set_option -fanout_limit 10000
add_file -constraint ${basepath}/src/xdc/clock_160.sdc
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
}
freq160retfan16 {
set_option -frequency 160
set_option -fanout_limit 16
add_file -constraint ${basepath}/src/xdc/clock_160.sdc
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
}
freq80retfan10000 {
set_option -frequency 80
set_option -fanout_limit 10000
add_file -constraint ${basepath}/src/xdc/clock_80.sdc
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
}
freq80retfan16 {
set_option -frequency 80
set_option -fanout_limit 16
add_file -constraint ${basepath}/src/xdc/clock_80.sdc
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
}
freq320retfan10000 {
set_option -frequency 320
set_option -fanout_limit 10000
add_file -constraint ${basepath}/src/xdc/clock_320.sdc
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
}
freq320retfan16 {
set_option -frequency 320
set_option -fanout_limit 16
add_file -constraint ${basepath}/src/xdc/clock_320.sdc
add_file -constraint ${basepath}/src/xdc/wrapper.sdc
}
default {
puts "Invalid opt option!"
}
}
hdl_param -set I $I
hdl_param -set O $O
hdl_param -set delay $D
project -save $prjpath
project -run compile
cd ${basepath}/syn
export_project -instance muon_sorter_1 -add_file {../src/rtl/MuctpiDataTypes.vhd ../src/rtl/MuctpiFunctions.vhd ../src/rtl/muon_sorter.vhd} -no_default_hdl -project $subprjpath
set_option -disable_io_insertion 1
set_option -part XCVU9P
set_option -package FLGC2104
set_option -vhdl2008 1
set_option -retiming 1
set_option -frequency 160
set_option -fanout_limit 16
hdl_param -set num_in $I
hdl_param -set num_out $O
hdl_param -set delay $D
set_option -job pr_1 -add par
set_option -job pr_1 -option enable_run 0
project_data -active $subprjpath
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
project -save $subprjpath
set_option -disable_io_insertion 1
set_option -part XCVU9P
set_option -package FLGC2104
set_option -vhdl2008 1
hdl_param -set num_in $I
hdl_param -set num_out $O
hdl_param -set delay $D
set_option -job pr_1 -add par
set_option -job pr_1 -option enable_run 0
switch $opt {
freq160retfan10000 {
set_option -retiming 1
set_option -frequency 160
set_option -fanout_limit 10000
add_file -constraint ${basepath}/src/xdc/clock_160.sdc
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
}
freq160retfan16 {
set_option -retiming 1
set_option -frequency 160
set_option -fanout_limit 16
add_file -constraint ${basepath}/src/xdc/clock_160.sdc
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
}
freq80retfan10000 {
set_option -retiming 1
set_option -frequency 80
set_option -fanout_limit 10000
add_file -constraint ${basepath}/src/xdc/clock_80.sdc
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
}
freq80retfan16 {
set_option -retiming 1
set_option -frequency 80
set_option -fanout_limit 16
add_file -constraint ${basepath}/src/xdc/clock_80.sdc
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
}
freq320retfan10000 {
set_option -retiming 1
set_option -frequency 320
set_option -fanout_limit 10000
add_file -constraint ${basepath}/src/xdc/clock_320.sdc
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
}
freq320retfan16 {
set_option -retiming 1
set_option -frequency 320
set_option -fanout_limit 16
add_file -constraint ${basepath}/src/xdc/clock_320.sdc
add_file -constraint ${basepath}/src/xdc/muon_sorter.sdc
}
default {
puts "Invalid opt option!"
}
}
project -save $subprjpath
project_data -active $prjpath
set_option -job par_1 -option enable_run 1
#impl -active rev_1
if {$run == 1} {project -run}
project -save $prjpath
project_data -active $prjpath
set_option -job par_1 -option enable_run 1
#impl -active rev_1
if {$run == 1} {project -run}
project -save $prjpath
}
proc range {from to {step 1}} {
set res $from; while {$to>$from} {lappend res [incr from $step]}; return $res
set res $from; while {$to>$from} {lappend res [incr from $step]}; return $res
}
set cfgs []
lappend cfgs [list 16 16 [range 0 5]]
lappend cfgs [list 32 16 [range 0 7]]
set cfgs []
set opts [list freq320retfan10000 freq320retfan16 freq160retfan10000 freq160retfan16 freq80retfan10000 freq80retfan16]
#lappend cfgs [list 16 16 [range 0 2]]
lappend cfgs [list 16 2 [range 0 2]]
#lappend cfgs [list 16 16 [range 0 5]]
#lappend cfgs [list 32 16 [range 0 7]]
#lappend cfgs [list 48 16 [range 0 8]]
#lappend cfgs [list 64 16 [range 0 10]]
foreach cfg $cfgs {
foreach {I O Dr} $cfg {
foreach {I O Dr} $cfg {
foreach {D} $Dr {
puts "$I $O $D"
create_run $I $O $D 1
foreach opt $opts {
puts "$I $O $D"
create_run $I $O $D 1 $opt
}
}
}
}
#run_tcl D:/mygitlab/sorting/src/tcl/generate_syn_runs.tcl
# project_data -active D:/mygitlab/sorting/syn/muon_sorter_muon_sorter_1/muon_sorter_muon_sorter_1.prj
# set_option -disable_io_insertion 1
# set_option -part XCVU9P
# set_option -package FLGC2104
# set_option -vhdl2008 1
# set_option -retiming 1
# hdl_param -set num_in 16
# hdl_param -set num_out 16
# hdl_param -set delay 0
# set_option -job pr_1 -add par
# set_option -job pr_1 -option enable_run 0
# set_option -constraint D:/mygitlab/sorting/src/xdc/muon_sorter.sdc
# project -save D:/mygitlab/sorting/syn/muon_sorter_muon_sorter_1/muon_sorter_muon_sorter_1.prj
#impl -active muon_impl
# project -run
# project_data -active D:/mygitlab/sorting/syn/prjI016O16D00/wrapperI016O16D00.prj
#impl -active wrapper_impl
# project -run
\ No newline at end of file
}
}
\ No newline at end of file
create_clock -period 6.250 -name clk -waveform {0.000 3.125} [get_ports clk]
set_input_delay 0 -clock clk muon_cand*
set_input_delay 0 -clock clk sink_valid
set_output_delay 0 -clock clk top_cand*
......
......@@ -11,10 +11,7 @@
define_attribute {v:muon_sorter_16_16_2} syn_hier {hard}
create_clock -period 1000.000 -name clk_wrapper -waveform {0.000 500.000} [get_ports clk_wrapper]
create_clock -period 6.250 -name clk_user -waveform {0.000 3.125} [get_ports clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_wrapper] -group [get_clocks clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_user] -group [get_clocks clk_wrapper]
set_clock_groups -asynchronous -group [get_clocks clk_wrapper] -group [get_clocks clk]
set_clock_groups -asynchronous -group [get_clocks clk] -group [get_clocks clk_wrapper]
set_false_path -from [get_clocks clk_wrapper] -to [get_clocks clk_wrapper]
# not investigating timing yet
#set_false_path -from [get_clocks clk_user] -to [get_clocks clk_user]
\ No newline at end of file
set_property PACKAGE_PIN AU33 [get_ports clk_wrapper]
set_property PACKAGE_PIN AV33 [get_ports clk_user]
set_property PACKAGE_PIN AV33 [get_ports clk]
set_property PACKAGE_PIN AN32 [get_ports input]
set_property PACKAGE_PIN AU31 [get_ports output]
set_property IOSTANDARD LVCMOS18 [get_ports clk_wrapper]
set_property IOSTANDARD LVCMOS18 [get_ports clk_user]
set_property IOSTANDARD LVCMOS18 [get_ports clk]
set_property IOSTANDARD LVCMOS18 [get_ports input]
set_property IOSTANDARD LVCMOS18 [get_ports output]
create_clock -period 1000.000 -name clk_wrapper -waveform {0.000 500.000} [get_ports clk_wrapper]
create_clock -period 6.250 -name clk_user -waveform {0.000 3.125} [get_ports clk_user]
create_clock -period 6.250 -name clk -waveform {0.000 3.125} [get_ports clk]
set_clock_groups -asynchronous -group [get_clocks clk_wrapper] -group [get_clocks clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_user] -group [get_clocks clk_wrapper]
set_clock_groups -asynchronous -group [get_clocks clk_wrapper] -group [get_clocks clk]
set_clock_groups -asynchronous -group [get_clocks clk] -group [get_clocks clk_wrapper]
set_false_path -from [get_clocks clk_wrapper] -to [get_clocks clk_wrapper]
# not investigating timing yet
#set_false_path -from [get_clocks clk_user] -to [get_clocks clk_user]
......
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