Commit 45f1a535 authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
Browse files

Results from short shift register

parent bf79fa34
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:31:10 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_high_fanout_nets -file fanout.txt -max_nets 200
| Design : wrapper
| Device : xcvu9p
------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+--------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+--------------------------------+--------+-------------+
| muon_sorter_1/max_pt_0[8] | 50 | LUT6 |
| muon_sorter_1/max_pt_0[7] | 46 | LUT6 |
| muon_sorter_1/max_pt_13[11] | 45 | LUT5 |
| muon_sorter_1/max_pt_1[6] | 45 | LUT6 |
| muon_sorter_1/max_pt_9[6] | 43 | LUT6 |
| muon_sorter_1/max_pt_14[13] | 42 | LUT5 |
| muon_sorter_1/max_pt_14[7] | 42 | LUT4 |
| muon_sorter_1/max_pt_14[9] | 42 | LUT6 |
| muon_sorter_1/max_pt_12[2] | 41 | LUT4 |
| muon_sorter_1/max_pt_12[5] | 40 | LUT6 |
| muon_sorter_1/max_pt_14[14] | 40 | LUT6 |
| muon_sorter_1/max_pt_14[6] | 40 | LUT6 |
| muon_sorter_1/max_pt_5[9] | 40 | LUT6 |
| muon_sorter_1/max_pt_0[9] | 39 | LUT6 |
| muon_sorter_1/max_pt_14[1] | 39 | LUT6 |
| muon_sorter_1/max_pt_1[3] | 39 | LUT5 |
| muon_sorter_1/max_pt_12[1] | 38 | LUT6 |
| muon_sorter_1/max_pt_14[3] | 38 | LUT6 |
| muon_sorter_1/max_pt_9[9] | 38 | LUT6 |
| muon_sorter_1/max_pt_14[5] | 37 | LUT6 |
| muon_sorter_1/max_pt_14[8] | 37 | LUT6 |
| muon_sorter_1/max_pt_9[1] | 37 | LUT6 |
| muon_sorter_1/max_pt_9[2] | 37 | LUT5 |
| muon_sorter_1/max_pt_12[15] | 36 | LUT6 |
| muon_sorter_1/max_pt_14[10] | 36 | LUT6 |
| muon_sorter_1/max_pt_14[11] | 36 | LUT6 |
| muon_sorter_1/max_pt_14[2] | 36 | LUT6 |
| muon_sorter_1/max_pt_14[4] | 36 | LUT6 |
| muon_sorter_1/max_pt_0[2] | 35 | LUT6 |
| muon_sorter_1/max_pt_10_1[14] | 35 | LUT6 |
| muon_sorter_1/max_pt_12[14] | 35 | LUT6 |
| muon_sorter_1/max_pt_3_1[14] | 35 | LUT6 |
| muon_sorter_1/max_pt_11_1[14] | 34 | LUT6 |
| muon_sorter_1/max_pt_12[8] | 34 | LUT6 |
| muon_sorter_1/max_pt_14[12] | 34 | LUT5 |
| muon_sorter_1/max_pt_1_0[14] | 34 | LUT6 |
| muon_sorter_1/max_pt_1_2[14] | 34 | LUT6 |
| muon_sorter_1/max_pt_2_1[14] | 34 | LUT5 |
| muon_sorter_1/max_pt_7[9] | 34 | LUT6 |
| muon_sorter_1/max_pt_10_0[14] | 33 | LUT6 |
| muon_sorter_1/max_pt_10_2[14] | 33 | LUT6 |
| muon_sorter_1/max_pt_12[7] | 33 | LUT6 |
| muon_sorter_1/max_pt_13_1[14] | 33 | LUT6 |
| muon_sorter_1/max_pt_14[15] | 33 | LUT6 |
| muon_sorter_1/max_pt_1_1[14] | 33 | LUT4 |
| muon_sorter_1/max_pt_9[5] | 33 | LUT6 |
| muon_sorter_1/max_pt_11_3[14] | 32 | LUT5 |
| muon_sorter_1/max_pt_2_0[14] | 32 | LUT6 |
| muon_sorter_1/max_pt_5[3] | 32 | LUT6 |
| muon_sorter_1/max_pt_6_1[14] | 32 | LUT6 |
| muon_sorter_1/max_pt_7_1[14] | 32 | LUT6 |
| muon_sorter_1/max_pt_8_1[14] | 32 | LUT6 |
| muon_sorter_1/max_pt_9_1[14] | 32 | LUT6 |
| muon_sorter_1/max_pt_0[10] | 31 | LUT6 |
| muon_sorter_1/max_pt_13_2[14] | 31 | LUT6 |
| muon_sorter_1/max_pt_5[4] | 31 | LUT6 |
| muon_sorter_1/max_pt_5_0[14] | 31 | LUT6 |
| muon_sorter_1/max_pt_5_1[14] | 31 | LUT5 |
| muon_sorter_1/max_pt_9[7] | 31 | LUT6 |
| muon_sorter_1/max_pt_0[1] | 30 | LUT5 |
| muon_sorter_1/max_pt_12[4] | 30 | LUT6 |
| muon_sorter_1/max_pt_13_0[14] | 30 | LUT6 |
| muon_sorter_1/max_pt_10[9] | 29 | LUT6 |
| muon_sorter_1/max_pt_12[6] | 29 | LUT6 |
| muon_sorter_1/max_pt_14[0] | 29 | LUT6 |
| muon_sorter_1/max_pt_7[8] | 29 | LUT6 |
| muon_sorter_1/max_pt_8_0[14] | 29 | LUT6 |
| muon_sorter_1/max_pt_8_2[14] | 29 | LUT6 |
| muon_sorter_1/max_pt_0_3[6] | 28 | LUT6 |
| muon_sorter_1/max_pt_10[15] | 28 | LUT5 |
| muon_sorter_1/max_pt_10[5] | 28 | LUT6 |
| muon_sorter_1/max_pt_10[7] | 28 | LUT6 |
| muon_sorter_1/max_pt_12[12] | 28 | LUT6 |
| muon_sorter_1/max_pt_12[3] | 28 | LUT6 |
| muon_sorter_1/max_pt_2_2[14] | 28 | LUT5 |
| muon_sorter_1/max_pt_3[10] | 28 | LUT6 |
| muon_sorter_1/max_pt_7_3[14] | 28 | LUT4 |
| muon_sorter_1/max_pt_9[0] | 28 | LUT6 |
| muon_sorter_1/max_pt_9[15] | 28 | LUT6 |
| muon_sorter_1/max_pt_2[4] | 27 | LUT6 |
| muon_sorter_1/max_pt_2[6] | 27 | LUT6 |
| muon_sorter_1/max_pt_5[12] | 27 | LUT6 |
| muon_sorter_1/max_pt_5_2[14] | 27 | LUT4 |
| muon_sorter_1/max_pt_7[4] | 27 | LUT6 |
| muon_sorter_1/max_pt_9[11] | 27 | LUT6 |
| muon_sorter_1/max_pt_9_3[14] | 27 | LUT6 |
| muon_sorter_1/max_pt_0[11] | 26 | LUT5 |
| muon_sorter_1/max_pt_12[0] | 26 | LUT6 |
| muon_sorter_1/max_pt_12[9] | 26 | LUT4 |
| muon_sorter_1/max_pt_3[3] | 26 | LUT6 |
| muon_sorter_1/max_pt_5[0] | 26 | LUT6 |
| muon_sorter_1/max_pt_5[6] | 26 | LUT6 |
| muon_sorter_1/max_pt_5[7] | 26 | LUT6 |
| muon_sorter_1/max_pt_6_0[14] | 26 | LUT5 |
| muon_sorter_1/max_pt_9[8] | 26 | LUT6 |
| muon_sorter_1/max_pt_0[0] | 25 | LUT3 |
| muon_sorter_1/max_pt_0_1[6] | 25 | LUT5 |
| muon_sorter_1/max_pt_10[4] | 25 | LUT6 |
| muon_sorter_1/max_pt_12[13] | 25 | LUT6 |
| muon_sorter_1/max_pt_13_1[12] | 25 | LUT6 |
| muon_sorter_1/max_pt_3[4] | 25 | LUT5 |
| muon_sorter_1/max_pt_5[2] | 25 | LUT6 |
| muon_sorter_1/max_pt_6_2[14] | 25 | LUT5 |
| muon_sorter_1/max_pt_13[15] | 24 | LUT6 |
| muon_sorter_1/max_pt_1[9] | 24 | LUT6 |
| muon_sorter_1/max_pt_2[11] | 24 | LUT6 |
| muon_sorter_1/max_pt_3[0] | 24 | LUT6 |
| muon_sorter_1/max_pt_3[6] | 24 | LUT6 |
| muon_sorter_1/max_pt_5[11] | 24 | LUT6 |
| muon_sorter_1/max_pt_5[5] | 24 | LUT6 |
| muon_sorter_1/max_pt_7[5] | 24 | LUT6 |
| muon_sorter_1/max_pt_9[10] | 24 | LUT6 |
| muon_sorter_1/max_pt_0_3[3] | 23 | LUT6 |
| muon_sorter_1/max_pt_10[11] | 23 | LUT6 |
| muon_sorter_1/max_pt_10[1] | 23 | LUT6 |
| muon_sorter_1/max_pt_10[3] | 23 | LUT6 |
| muon_sorter_1/max_pt_11[11] | 23 | LUT6 |
| muon_sorter_1/max_pt_13_3[12] | 23 | LUT5 |
| muon_sorter_1/max_pt_1[0] | 23 | LUT6 |
| muon_sorter_1/max_pt_1_1[2] | 23 | LUT6 |
| muon_sorter_1/max_pt_3[11] | 23 | LUT5 |
| muon_sorter_1/max_pt_3_0_4[14] | 23 | LUT6 |
| muon_sorter_1/max_pt_3_1_3[14] | 23 | LUT6 |
| muon_sorter_1/max_pt_7[0] | 23 | LUT6 |
| muon_sorter_1/max_pt_7[2] | 23 | LUT6 |
| muon_sorter_1/max_pt_7[3] | 23 | LUT5 |
| muon_sorter_1/max_pt_8[6] | 23 | LUT6 |
| muon_sorter_1/max_pt_0_1[3] | 22 | LUT5 |
| muon_sorter_1/max_pt_0_3[5] | 22 | LUT6 |
| muon_sorter_1/max_pt_12[10] | 22 | LUT5 |
| muon_sorter_1/max_pt_1[10] | 22 | LUT6 |
| muon_sorter_1/max_pt_1[8] | 22 | LUT6 |
| muon_sorter_1/max_pt_2[15] | 22 | LUT6 |
| muon_sorter_1/max_pt_2[9] | 22 | LUT6 |
| muon_sorter_1/max_pt_3[9] | 22 | LUT5 |
| muon_sorter_1/max_pt_5[15] | 22 | LUT6 |
| muon_sorter_1/max_pt_7[1] | 22 | LUT6 |
| muon_sorter_1/max_pt_9[4] | 22 | LUT6 |
| muon_sorter_1/max_pt_0[3] | 21 | LUT6 |
| muon_sorter_1/max_pt_0_1[5] | 21 | LUT5 |
| muon_sorter_1/max_pt_0_3[14] | 21 | LUT6 |
| muon_sorter_1/max_pt_10[2] | 21 | LUT5 |
| muon_sorter_1/max_pt_10[8] | 21 | LUT6 |
| muon_sorter_1/max_pt_13[2] | 21 | LUT6 |
| muon_sorter_1/max_pt_13[7] | 21 | LUT6 |
| muon_sorter_1/max_pt_13_1[13] | 21 | LUT6 |
| muon_sorter_1/max_pt_1[15] | 21 | LUT4 |
| muon_sorter_1/max_pt_1[1] | 21 | LUT4 |
| muon_sorter_1/max_pt_1[4] | 21 | LUT6 |
| muon_sorter_1/max_pt_1_1[12] | 21 | LUT6 |
| muon_sorter_1/max_pt_2[3] | 21 | LUT6 |
| muon_sorter_1/max_pt_3[5] | 21 | LUT6 |
| muon_sorter_1/max_pt_4[3] | 21 | LUT6 |
| muon_sorter_1/max_pt_4[4] | 21 | LUT6 |
| muon_sorter_1/max_pt_5[13] | 21 | LUT6 |
| muon_sorter_1/max_pt_5[1] | 21 | LUT6 |
| muon_sorter_1/max_pt_5_0[2] | 21 | LUT6 |
| muon_sorter_1/max_pt_5_1[2] | 21 | LUT5 |
| muon_sorter_1/max_pt_6[2] | 21 | LUT5 |
| muon_sorter_1/max_pt_7[13] | 21 | LUT6 |
| muon_sorter_1/max_pt_0_0[13] | 20 | LUT6 |
| muon_sorter_1/max_pt_0_0[15] | 20 | LUT6 |
| muon_sorter_1/max_pt_0_1[0] | 20 | LUT5 |
| muon_sorter_1/max_pt_0_1[13] | 20 | LUT5 |
| muon_sorter_1/max_pt_0_1[14] | 20 | LUT5 |
| muon_sorter_1/max_pt_0_1[15] | 20 | LUT5 |
| muon_sorter_1/max_pt_0_3[4] | 20 | LUT6 |
| muon_sorter_1/max_pt_10[12] | 20 | LUT4 |
| muon_sorter_1/max_pt_11[8] | 20 | LUT6 |
| muon_sorter_1/max_pt_11[9] | 20 | LUT6 |
| muon_sorter_1/max_pt_11_1[15] | 20 | LUT6 |
| muon_sorter_1/max_pt_12_0[13] | 20 | LUT6 |
| muon_sorter_1/max_pt_12_1[13] | 20 | LUT5 |
| muon_sorter_1/max_pt_13[10] | 20 | LUT6 |
| muon_sorter_1/max_pt_13[4] | 20 | LUT6 |
| muon_sorter_1/max_pt_13[5] | 20 | LUT6 |
| muon_sorter_1/max_pt_13_1[0] | 20 | LUT6 |
| muon_sorter_1/max_pt_1[2] | 20 | LUT6 |
| muon_sorter_1/max_pt_1[7] | 20 | LUT5 |
| muon_sorter_1/max_pt_1_0[12] | 20 | LUT6 |
| muon_sorter_1/max_pt_2[12] | 20 | LUT6 |
| muon_sorter_1/max_pt_2_0[10] | 20 | LUT6 |
| muon_sorter_1/max_pt_2_1[10] | 20 | LUT5 |
| muon_sorter_1/max_pt_4[6] | 20 | LUT6 |
| muon_sorter_1/max_pt_6[11] | 20 | LUT4 |
| muon_sorter_1/max_pt_7[10] | 20 | LUT6 |
| muon_sorter_1/max_pt_9[13] | 20 | LUT6 |
| muon_sorter_1/max_pt_9[3] | 20 | LUT6 |
| muon_sorter_1/max_pt_9_1[12] | 20 | LUT5 |
| muon_sorter_1/max_pt_9_1[8] | 20 | LUT5 |
| muon_sorter_1/max_pt_0[12] | 19 | LUT6 |
| muon_sorter_1/max_pt_0[13] | 19 | LUT6 |
| muon_sorter_1/max_pt_0[14] | 19 | LUT6 |
| muon_sorter_1/max_pt_0[5] | 19 | LUT6 |
| muon_sorter_1/max_pt_10[0] | 19 | LUT5 |
| muon_sorter_1/max_pt_10_1_1[3] | 19 | LUT5 |
| muon_sorter_1/max_pt_11[10] | 19 | LUT6 |
| muon_sorter_1/max_pt_11[2] | 19 | LUT6 |
| muon_sorter_1/max_pt_11_1[11] | 19 | LUT6 |
| muon_sorter_1/max_pt_11_1[2] | 19 | LUT5 |
+--------------------------------+--------+-------------+
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:31:10 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_high_fanout_nets -histogram -file fanout_hist.txt
| Design : wrapper
| Device : xcvu9p
------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Histogram
------------
+---------+------+--------+
| Fanout | Nets | % |
+---------+------+--------+
| 1 | 4796 | 55.23 |
| 2 | 690 | 7.94 |
| 3 | 530 | 6.10 |
| 4 | 529 | 6.09 |
| 5-10 | 1175 | 13.53 |
| 11-50 | 963 | 11.09 |
| 51-100 | 0 | 0.00 |
| 101-500 | 0 | 0.00 |
| >500 | 0 | 0.00 |
+---------+------+--------+
| ALL | 8683 | 100.00 |
+---------+------+--------+
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:28:41 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_utilization -hierarchical -file hier_utilization.txt
| Design : wrapper
| Device : xcvu9pflgc2104-1
| Design State : Routed
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Utilization by Hierarchy
1. Utilization by Hierarchy
---------------------------
+-------------------+-------------------------------------------------------------+------------+------------+---------+------+------+--------+--------+------+--------------+
| Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | URAM | DSP48 Blocks |
+-------------------+-------------------------------------------------------------+------------+------------+---------+------+------+--------+--------+------+--------------+
| wrapper | (top) | 6012 | 6012 | 0 | 0 | 2567 | 0 | 0 | 0 | 0 |
| (wrapper) | (top) | 0 | 0 | 0 | 0 | 434 | 0 | 0 | 0 | 0 |
| lsfr_1 | lfsr | 1 | 1 | 0 | 0 | 257 | 0 | 0 | 0 | 0 |
| muon_sorter_1 | muon_sorter_I016_O016_D000_SHORTSR-freq160retfan10000_rev_1 | 5926 | 5926 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| reducer_1 | reducer | 85 | 85 | 0 | 0 | 340 | 0 | 0 | 0 | 0 |
| shift_reg_tap_i | shift_reg_tap_256_2 | 0 | 0 | 0 | 0 | 768 | 0 | 0 | 0 | 0 |
| shift_reg_tap_o | shift_reg_tap_256_2_0 | 0 | 0 | 0 | 0 | 768 | 0 | 0 | 0 | 0 |
+-------------------+-------------------------------------------------------------+------------+------------+---------+------+------+--------+--------+------+--------------+
* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:29:31 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_drc -file post_route_drc.txt
| Design : wrapper
| Device : xcvu9p-flgc2104-1-e
| Speed File : -1
| Design State : Routed
------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:28:43 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_utilization -slr -file slr.txt
| Design : wrapper
| Device : xcvu9pflgc2104-1
| Design State : Routed
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. SLR Connectivity and Clocking Utilization
2. SLR Connectivity Matrix
3. SLR CLB Logic and Dedicated Block Utilization
4. SLR IO Utilization
1. SLR Connectivity and Clocking Utilization
--------------------------------------------
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| | Total SLLs Used | (%)SLLs | BUFGs/BUFGCTRLs | BUFH/BUFHCEs | BUFRs | MMCMs |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| SLR2 | | | 0 | 0 | 0 | 0 |
| ||||||-> | 0 | 0.00 | | | | |
| SLR1 | | | 2 | 0 | 0 | 0 |
| ||||||-> | 0 | 0.00 | | | | |
| SLR0 | | | 0 | 0 | 0 | 0 |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| Total | 0 | | 2 | 0 | 0 | 0 |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
2. SLR Connectivity Matrix
--------------------------
+------+------+------+------+
| | SLR2 | SLR1 | SLR0 |
+------+------+------+------+
| SLR2 | 0 | 0 | 0 |
| SLR1 | 0 | 0 | 0 |
| SLR0 | 0 | 0 | 0 |
+------+------+------+------+
3. SLR CLB Logic and Dedicated Block Utilization
------------------------------------------------
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
| SLR Index | CLBs | (%)CLBs | Total LUTs | Memory LUTs | (%)Total LUTs | Registers | BRAMs | URAM | DSPs |
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
| SLR2 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0 | 0 |
| SLR1 | 1002 | 2.03 | 6012 | 0 | 1.53 | 2567 | 0 | 0 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0 | 0.00 | 0 | 0 | 0 | 0 |
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
| Total | 1002 | | 6012 | 0 | | 2567 | 0 | 0 | 0 |
+-----------+------+---------+------------+-------------+---------------+-----------+-------+------+------+
4. SLR IO Utilization
---------------------
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
| SLR Index | Bonded IOBs | (%)IOBs | Bonded IPADs | (%)IPADs | Bonded OPADs | (%)OPADs | GTs |
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
| SLR2 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR1 | 4 | 1.54 | 0 | 0.00 | 0 | 0.00 | 0 |
| SLR0 | 0 | 0.00 | 0 | 0.00 | 0 | 0.00 | 0 |
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
| Total | 4 | | 0 | | 0 | | 0 |
+-----------+-------------+---------+--------------+----------+--------------+----------+-----+
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:29:31 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_clock_interaction -file wrapper_clock_interaction.rpt
| Design : wrapper
| Device : xcvu9p-flgc2104
| Speed File : -1 PRODUCTION 1.20 05-21-2018
| Temperature Grade : E
-----------------------------------------------------------------------------------------
Clock Interaction Report
Clock Interaction Table
-----------------------
WNS TNS Failing TNS Total WNS Path Clock-Pair Inter-Clock
From Clock To Clock Clock Edges WNS(ns) TNS(ns) Endpoints Endpoints Requirement(ns) Classification Constraints
------------ ------------ ----------- ------- -------- ----------- ----------- --------------- ------------------- -------------------
clk clk rise - rise -13.18 -1517.33 222 1714 6.25 Clean Timed
clk clk_wrapper 0 256 Ignored Asynchronous Groups
clk_wrapper clk 0 256 Ignored Asynchronous Groups
clk_wrapper clk_wrapper 0 342 Ignored False Path
#-- Synopsys, Inc.
#-- Version O-2018.09
#-- Project file D:\mygitlab\sorting\syn\I016_O016_D000_SHORTSR-freq160retfan10000\rev_1\run_options.txt
#-- Written on Thu Feb 14 12:03:04 2019
#project files
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/MuctpiDataTypes.vhd"
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/MuctpiFunctions.vhd"
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/muon_sorter.vhd"
add_file -constraint "D:/mygitlab/sorting/src/xdc/clock_160.sdc"
add_file -constraint "D:/mygitlab/sorting/src/xdc/muon_sorter.sdc"
#implementation: "rev_1"
impl -add rev_1 -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#
#implementation parameter settings
set_option -hdl_param -set I 16
set_option -hdl_param -set O 16
set_option -hdl_param -set delay 0
set_option -hdl_param -set num_in 16
set_option -hdl_param -set num_out 16
set_option -include_path {../}
set_option -library_path {../}
#pr_1 attributes
set_option -job pr_1 -add par
#device options
set_option -technology VIRTEX-ULTRASCALEPLUS-FPGAS
set_option -part XCVU9P
set_option -package FLGC2104
set_option -speed_grade -1-e
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.muon_sorter"
# hdl_compiler_options
set_option -distributed_compile 1
# mapper_without_write_options
set_option -frequency 160
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 1
set_option -write_vhdl 0
# xilinx_options
set_option -rw_check_on_ram 1
set_option -optimize_ngc 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Virtex UltraScale+ FPGAs
set_option -enable_prepacking 1
set_option -use_vivado 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
# Compiler Options
set_option -vhdl2008 1
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "../rev_1/muon_sorter.edf"
#design plan options
impl -active "rev_1"
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Thu Feb 14 12:02:43 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_high_fanout_nets -file fanout.txt -max_nets 200
| Design : wrapper
| Device : xcvu9p
------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+-----------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+-----------------------------------+--------+-------------+
| muon_sorter_1/max_pt_0[8] | 49 | LUT6 |
| muon_sorter_1/max_pt_0[7] | 48 | LUT6 |
| muon_sorter_1/max_pt_1[6] | 48 | LUT6 |
| muon_sorter_1/max_pt_9[6] | 48 | LUT6 |
| muon_sorter_1/max_pt_10[7] | 46 | LUT6 |
| muon_sorter_1/max_pt_12[15] | 46 | LUT4 |
| muon_sorter_1/max_pt_12[5] | 44 | LUT6 |
| muon_sorter_1/max_pt_14[11] | 43 | LUT6 |
| muon_sorter_1/max_pt_12[2] | 42 | LUT4 |
| muon_sorter_1/max_pt_14[0] | 42 | LUT6 |
| muon_sorter_1/max_pt_14[6] | 42 | LUT5 |
| muon_sorter_1/max_pt_12[1] | 41 | LUT6 |
| muon_sorter_1/max_pt_14[14] | 41 | LUT6 |
| muon_sorter_1/max_pt_9[9] | 41 | LUT6 |
| muon_sorter_1/max_pt_0[10] | 40 | LUT6 |
| muon_sorter_1/max_pt_14[4] | 40 | LUT6 |
| muon_sorter_1/max_pt_14[5] | 39 | LUT6 |
| muon_sorter_1/max_pt_5[9] | 39 | LUT6 |
| muon_sorter_1/max_pt_11_1[14] | 38 | LUT6 |
| muon_sorter_1/max_pt_12[8] | 38 | LUT6 |
| muon_sorter_1/max_pt_14[10] | 38 | LUT6 |
| muon_sorter_1/max_pt_14[7] | 38 | LUT6 |
| muon_sorter_1/max_pt_9[1] | 38 | LUT6 |
| muon_sorter_1/max_pt_13_1[14] | 37 | LUT6 |
| muon_sorter_1/max_pt_14[12] | 37 | LUT6 |
| muon_sorter_1/max_pt_14[1] | 37 | LUT6 |
| muon_sorter_1/max_pt_14[8] | 37 | LUT6 |
| muon_sorter_1/max_pt_1[3] | 37 | LUT6 |
| muon_sorter_1/max_pt_3_1[14] | 37 | LUT6 |
| muon_sorter_1/max_pt_9[2] | 37 | LUT6 |
| muon_sorter_1/max_pt_9_1[14] | 37 | LUT6 |
| muon_sorter_1/max_pt_0[2] | 36 | LUT6 |
| muon_sorter_1/max_pt_13_0[14] | 36 | LUT6 |
| muon_sorter_1/max_pt_13_2[14] | 36 | LUT6 |
| muon_sorter_1/max_pt_14[3] | 36 | LUT5 |
| muon_sorter_1/max_pt_4_1[14] | 36 | LUT6 |
| muon_sorter_1/max_pt_7[9] | 36 | LUT6 |
| muon_sorter_1/max_pt_12[14] | 35 | LUT6 |
| muon_sorter_1/max_pt_12[4] | 35 | LUT6 |