Added shift register for muon sorter inputs to see if it changes I/O retiming bottlenecks.

src/rtl/muon_sorter.vhd

@@ -60,7 +60,7 @@ architecture behavior of muon_sorter is
 	signal top_cand_comb : MuonCandidateArray(0 to num_out - 1);
 	
 
-	-- pipeline
+	-- pipeline output
 	
 	
 	type sr_t is array (integer range <>) of MuonCandidateArray(0 to num_out - 1);
@@ -74,18 +74,35 @@ architecture behavior of muon_sorter is
 	attribute syn_srlstyle: string;  
     attribute syn_srlstyle of sr : signal is "registers";
     attribute syn_srlstyle of sr_v : signal is "registers";
+    
+   -- pipeline input
+   
+   	type in_sr_t is array (integer range <>) of MuonCandidateArray(0 to num_in - 1);
+	signal in_sr : sr_t(0 to delay);
+	signal in_sr_v : std_logic_vector(0 to delay);
+
+	attribute shreg_extract : string;
+	attribute shreg_extract of in_sr : signal is "no";
+	attribute shreg_extract of in_sr_v : signal is "no";
+	
+	attribute syn_srlstyle: string;  
+    attribute syn_srlstyle of in_sr : signal is "registers";
+    attribute syn_srlstyle of in_sr_v : signal is "registers";
+    
+    signal muon_cand_sr    : MuonCandidateArray(0 to num_in - 1);
+    signal sink_valid_sr : std_logic;
 
 begin
 
 	compare_p : process(all) is
 	begin                               -- process
 	-- generate a comparison matrix
-		for i in muon_cand'range loop
-			for j in muon_cand'range loop
+		for i in muon_cand_sr'range loop
+			for j in muon_cand_sr'range loop
 				-- generate the first half of the comparison matrix
 				if j < i then
 					-- comparison matrix for the top candidate
-					pt_compare(0)(i)(j) <= compare_pt(muon_cand(i).pt, muon_cand(j).pt);
+					pt_compare(0)(i)(j) <= compare_pt(muon_cand_sr(i).pt, muon_cand_sr(j).pt);
 					-- derive the matrices for the next higher candidates
 					for k in 1 to num_out - 1 loop
 						-- invert the comparison result if either candidate is the highest one
@@ -113,13 +130,13 @@ begin
 	-- assign the highset pt candidate index to the corresponding output
 		for k in top_cand'range loop
 			muon             := (sector => X"0", pt => X"0", roi => X"00");
-			for i in muon_cand'range loop
+			for i in muon_cand_sr'range loop
 				-- there can only be one highest pt candidate, so ne can use a logical OR to implement a multiplexer
 				--        enable := pt_compare(k)(i) ?= all_greater;
 				enable      := max_pt(k)(i);
-				muon.pt     := muon.pt or (enable and muon_cand(i).pt);
-				muon.sector := muon.sector or (enable and muon_cand(i).sector);
-				muon.roi    := muon.roi or (enable and muon_cand(i).roi);
+				muon.pt     := muon.pt or (enable and muon_cand_sr(i).pt);
+				muon.sector := muon.sector or (enable and muon_cand_sr(i).sector);
+				muon.roi    := muon.roi or (enable and muon_cand_sr(i).roi);
 			end loop;
 			top_cand_comb(k) <= muon;
 		end loop;                       -- k
@@ -128,17 +145,33 @@ begin
 
 	sr_p : process(all) is
 	begin
-		sr(0)   <= top_cand_comb;
-		sr_v(0) <= sink_valid;
 		if rising_edge(clk) then
 			for i in 1 to delay loop
 				sr(i)   <= sr(i - 1);
 				sr_v(i) <= sr_v(i - 1);
 			end loop;
 		end if;
-	end process sr_p;
 
+
+
+		if rising_edge(clk) then
+			for i in 1 to delay loop
+				in_sr(i)   <= sr(i - 1);
+				in_sr_v(i) <= sr_v(i - 1);
+			end loop;
+		end if;
+	end process sr_p;
+	
+	sr(0)   <= top_cand_comb;
+	sr_v(0) <= sink_valid_sr;
+		
+	in_sr(0)   <= muon_cand;
+	in_sr_v(0) <= sink_valid;
+	
 	top_cand     <= sr(delay);
 	source_valid <= sr_v(delay);
 
+	muon_cand_sr     <= in_sr(delay);
+	sink_valid_sr <= in_sr_v(delay);
+
 end behavior;
\ No newline at end of file

src/rtl/mux/mux.vhd

-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity mux is
-	generic(
-		AW    : natural := 12;
-		DW    : natural := 32;
-		delay : natural := 3            -- delay in clock cycles for pipeline register
-	);
-	port(
-		clk          : in  std_logic;
-		sel          : out std_logic_vector(AW - 1 downto 0);
-		input        : in  std_logic_vector(DW * (2**AW) - 1 downto 0);
-		sink_valid   : in  std_logic;
-		source_valid : out std_logic;
-		output       : out std_logic_vector(DW - 1 downto 0)
-	);
-end entity mux;
-
-architecture RTL of mux is
-
-	signal sel_int     : integer range 0 to 2**AW - 1;
-	signal output_comb : std_logic_vector(DW - 1 downto 0);
-
-	-- pipeline
-
-	type sr_t is array (integer range <>) of std_logic_vector(DW - 1 downto 0);
-	signal sr   : sr_t(0 to delay);
-	signal sr_v : std_logic_vector(0 to delay);
-
-	attribute shreg_extract : string;
-	attribute shreg_extract of sr : signal is "no";
-	attribute shreg_extract of sr_v : signal is "no";
-
-	attribute syn_srlstyle : string;
-	attribute syn_srlstyle of sr : signal is "registers";
-	attribute syn_srlstyle of sr_v : signal is "registers";
-
-begin
-
-	sel_int     <= to_integer(unsigned(sel));
-	output_comb <= input((sel_int + 1) * DW - 1 downto sel_int * DW);
-
-	sr_p : process(all) is
-	begin
-		sr(0)   <= output_comb;
-		sr_v(0) <= sink_valid;
-		if rising_edge(clk) then
-			for i in 1 to delay loop
-				sr(i)   <= sr(i - 1);
-				sr_v(i) <= sr_v(i - 1);
-			end loop;
-		end if;
-	end process sr_p;
-
-	output       <= sr(delay);
-	source_valid <= sr_v(delay);
-
-end architecture RTL;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mux is
+	generic(
+		AW    : natural := 12;
+		DW    : natural := 32;
+		delay : natural := 3            -- delay in clock cycles for pipeline register
+	);
+	port(
+		clk          : in  std_logic;
+		sel          : out std_logic_vector(AW - 1 downto 0);
+		input        : in  std_logic_vector(DW * (2**AW) - 1 downto 0);
+		sink_valid   : in  std_logic;
+		source_valid : out std_logic;
+		output       : out std_logic_vector(DW - 1 downto 0)
+	);
+end entity mux;
+
+architecture RTL of mux is
+
+	signal sel_int     : integer range 0 to 2**AW - 1;
+	signal output_comb : std_logic_vector(DW - 1 downto 0);
+
+	-- pipeline
+
+	type sr_t is array (integer range <>) of std_logic_vector(DW - 1 downto 0);
+	signal sr   : sr_t(0 to delay);
+	signal sr_v : std_logic_vector(0 to delay);
+
+	attribute shreg_extract : string;
+	attribute shreg_extract of sr : signal is "no";
+	attribute shreg_extract of sr_v : signal is "no";
+
+	attribute syn_srlstyle : string;
+	attribute syn_srlstyle of sr : signal is "registers";
+	attribute syn_srlstyle of sr_v : signal is "registers";
+
+begin
+
+	sel_int     <= to_integer(unsigned(sel));
+	output_comb <= input((sel_int + 1) * DW - 1 downto sel_int * DW);
+
+	sr_p : process(all) is
+	begin
+		sr(0)   <= output_comb;
+		sr_v(0) <= sink_valid;
+		if rising_edge(clk) then
+			for i in 1 to delay loop
+				sr(i)   <= sr(i - 1);
+				sr_v(i) <= sr_v(i - 1);
+			end loop;
+		end if;
+	end process sr_p;
+
+	output       <= sr(delay);
+	source_valid <= sr_v(delay);
+
+end architecture RTL;
\ No newline at end of file

src/tcl/generate_syn_runs.tcl

 proc create_run {I O D {run 1} opt} {
     puts "Creating run with I = $I, O = $O, D = $D"
-    set prjpre [format "I%03d_O%03d_D%03d" $I $O $D]
+    set prjpre [format "I%03d_O%03d_D%03d_IORET" $I $O $D]
     set prjname [format "%s-%s" $prjpre $opt]
     set basepath "D:/mygitlab/sorting"
     set prjpath [format "%s/syn/%s/wrapper_%s.prj" $basepath $prjname $prjname]
@@ -173,9 +173,9 @@ set cfgs []
 set opts [list freq320retfan10000 freq320retfan16 freq160retfan10000 freq160retfan16 freq80retfan10000 freq80retfan16 freq40retfan10000 freq40retfan16]
 #lappend cfgs [list 16 16 [range 0 2]]
 #lappend cfgs [list 16 2 [range 0 2]]
-#lappend cfgs [list 16 16 [range 0 5]]
-lappend cfgs [list 32 16 [range 0 5]]
-lappend cfgs [list 32 4 [range 0 5]]
+lappend cfgs [list 16 16 [range 0 3]]
+#lappend cfgs [list 32 16 [range 0 5]]
+#lappend cfgs [list 32 4 [range 0 5]]
 #lappend cfgs [list 48 16 [range 0 8]]
 #lappend cfgs [list 64 16 [range 0 10]]
 

src/tcl/generate_syn_runs_mux.tcl

+proc create_run {AW DW D {run 1} opt} {
+    puts "Creating run with AW = $AW, DW = $DW, D = $D"
+    set prjpre [format "AW%03d_DW%03d_D%03d" $AW $DW $D]
+    set prjname [format "%s-%s" $prjpre $opt]
+    set basepath "D:/mygitlab/sorting"
+    set prjpath [format "%s/syn/%s/wrapper_mux_%s.prj" $basepath $prjname $prjname]
+    set subprjpath [format "%s/syn/%s/mux_1/mux_%s.prj" $basepath $prjname $prjname]
+    puts $prjpath
+    puts $subprjpath
+    project -new $prjpath
+    add_file -vhdl ${basepath}/src/rtl/mux/mux.vhd
+    add_file -verilog ${basepath}/src/rtl/lfsr.sv    
+    add_file -verilog ${basepath}/src/rtl/reducer.sv
+    add_file -vhdl ${basepath}/src/rtl/shift_reg_tap.vhd    
+	add_file -vhdl ${basepath}/src/rtl/mux/wrapper_mux.vhd  
+    set_option -disable_io_insertion 0
+    set_option -part XCVU9P
+    set_option -package FLGC2104
+    set_option -vhdl2008 1
+    set_option -retiming 0
+    switch $opt {
+	freq160retfan10000 {
+	    set_option -frequency 160
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_160.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq160retfan16 {
+	    set_option -frequency 160
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_160.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq80retfan10000 {
+	    set_option -frequency 80
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_80.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq80retfan16 {
+	    set_option -frequency 80
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_80.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq320retfan10000 {
+	    set_option -frequency 320
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_320.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq320retfan16 {
+	    set_option -frequency 320
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_320.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq40retfan10000 {
+	    set_option -frequency 40
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_40.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}
+	freq40retfan16 {
+	    set_option -frequency 40
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_40.sdc
+		add_file -constraint ${basepath}/src/xdc/wrapper.sdc
+	}	
+	default {
+	    puts "Invalid opt option!"
+	}
+    }
+    hdl_param -set AW $AW
+    hdl_param -set DW $DW
+    hdl_param -set delay $D
+    project -save $prjpath
+    project -run compile
+    cd ${basepath}/syn
+    export_project -instance mux_1 -add_file {../src/rtl/mux/mux.vhd} -no_default_hdl -project $subprjpath
+
+    project_data -active $subprjpath
+
+    set_option -disable_io_insertion 1
+    set_option -part XCVU9P
+    set_option -package FLGC2104
+    set_option -vhdl2008 1   
+    hdl_param -set AW $AW
+    hdl_param -set DW $DW
+    hdl_param -set delay $D
+    set_option -job pr_1 -add par
+    set_option -job pr_1 -option enable_run 0
+    switch $opt {
+	freq160retfan10000 {
+	    set_option -retiming 1
+	    set_option -frequency 160
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_160.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}
+	freq160retfan16 {
+	    set_option -retiming 1
+	    set_option -frequency 160
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_160.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}
+	freq80retfan10000 {
+	    set_option -retiming 1
+	    set_option -frequency 80
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_80.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}
+	freq80retfan16 {
+	    set_option -retiming 1
+	    set_option -frequency 80
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_80.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}	
+	freq320retfan10000 {
+	    set_option -retiming 1
+	    set_option -frequency 320
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_320.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}
+	freq320retfan16 {
+	    set_option -retiming 1
+	    set_option -frequency 320
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_320.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}
+	freq40retfan10000 {
+	    set_option -retiming 1
+	    set_option -frequency 40
+	    set_option -fanout_limit 10000
+		add_file -constraint ${basepath}/src/xdc/clock_40.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}
+	freq40retfan16 {
+	    set_option -retiming 1
+	    set_option -frequency 40
+	    set_option -fanout_limit 16
+		add_file -constraint ${basepath}/src/xdc/clock_40.sdc
+		add_file -constraint ${basepath}/src/xdc/mux.sdc
+	}	
+	default {
+	    puts "Invalid opt option!"
+	}
+    }
+
+    
+    project -save $subprjpath
+
+    project_data -active $prjpath
+    set_option -job par_1 -option enable_run 1
+    #impl -active rev_1
+    if {$run == 1} {project -run}  
+    project -save $prjpath
+}
+
+
+proc range {from to {step 1}} {
+    set res $from; while {$to>$from} {lappend res [incr from $step]}; return $res
+}
+
+set cfgs []
+set opts [list freq320retfan10000 freq320retfan16 freq160retfan10000 freq160retfan16 freq80retfan10000 freq80retfan16 freq40retfan10000 freq40retfan16]
+lappend cfgs [list 12 32 [range 0 3]]
+
+foreach cfg $cfgs {
+    foreach {AW DW Dr} $cfg {
+		foreach {D} $Dr {
+			foreach opt $opts {
+				puts "$AW $DW $D"
+				create_run $AW $DW $D 1 $opt
+			}
+		}
+    }
+}
\ No newline at end of file