Commit 84c24560 authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
Browse files

Multiplexor source code and testing.

parent e5fcbe18
......@@ -6,13 +6,13 @@ basepaths = glob.glob('../syn/*')
basepaths.sort()
extract_info = []
extract_info.append({'name': 'LUTs',
'rexp': ur"muon_sorter_1\s+(?:\|[^\|]+){1}\|\s+(\d+)",
'file': '/rev_1/par_1/hier_utilization.txt'})
extract_info.append({'name': 'FFs',
'rexp': ur"muon_sorter_1\s+(?:\|[^\|]+){5}\|\s+(\d+)",
'file': '/rev_1/par_1/hier_utilization.txt'})
# extract_info.append({'name': 'LUTs',
# 'rexp': ur"muon_sorter_1\s+(?:\|[^\|]+){1}\|\s+(\d+)",
# 'file': '/rev_1/par_1/hier_utilization.txt'})
#
# extract_info.append({'name': 'FFs',
# 'rexp': ur"muon_sorter_1\s+(?:\|[^\|]+){5}\|\s+(\d+)",
# 'file': '/rev_1/par_1/hier_utilization.txt'})
extract_info.append({'name': 'Logic Levels',
'rexp': ur"Logic Levels\s+(?:\|[^\|]+){1}\|\s+(\d+)",
......
This diff is collapsed.
package bitonic_sorter_pkg;
const integer ASCENDING = 1;
const integer DESCENDING = 0;
parameter int MUON_NUMBER = 352; // 16
parameter int IDX_WIDTH = $clog2(MUON_NUMBER);
parameter int PT_WIDTH = 4;
typedef struct {
logic [PT_WIDTH-1:0] pt;
logic [IDX_WIDTH-1:0] idx;
} muon_t;
endpackage : bitonic_sorter_pkg
library ieee;
use ieee.std_logic_1164.all;
use IEEE.math_real.all;
package bitonic_sorter_pkg is
constant ASCENDING : integer := 1;
constant DESCENDING : integer := 1;
constant MUON_NUMBER : integer := 352;
constant IDX_WIDTH : integer := integer(ceil(log(real(MUON_NUMBER), real(2))));
constant PT_WIDTH : integer := 4;
constant word_w : integer := PT_WIDTH+IDX_WIDTH;
type muon_t is record
idx : std_logic_vector(IDX_WIDTH-1 downto 0);
pt : std_logic_vector(PT_WIDTH-1 downto 0);
end record;
type muon_a is array (natural range <>) of muon_t;
function to_array(data : std_logic_vector; AW : integer; DW : integer) return muon_a;
end bitonic_sorter_pkg;
package body bitonic_sorter_pkg is
function to_array(data : std_logic_vector; N : integer) return muon_a is
variable muon : muon_a(0 to N-1);
begin
for i in muon'range loop
muon(i).pt := data((i+1)*word_w-1-IDX_WIDTH downto i*word_w);
muon(i).idx := data((i+1)*word_w-1 downto i*word_w+PT_WIDTH);
end loop;
return muon;
end to_array;
function to_stdv(muon : muon_a; N : integer) return std_logic_vector is
variable vector : std_logic_vector(N*word_w-1 downto 0);
begin
for i in muon'range loop
vector((i+1)*word_w-1-IDX_WIDTH downto i*word_w):= muon(i).pt;
vector((i+1)*word_w-1 downto i*word_w+PT_WIDTH) := muon(i).idx;
end loop;
return vector;
end to_stdv;
end package bitonic_sorter_pkg;
......@@ -156,7 +156,7 @@ begin -- architecture rtl
end if;
end process;
muon_cand_c <= to_muon(input_slr, I);
muon_cand_c <= to_array(input_slr, I);
output_vector(O*MuonCandidateLength-1 downto 0) <= to_stdv(top_cand, O);
muon_sorter_1 : entity work.muon_sorter
......
----------------------------------------------------------------------------------------------------------------------
-- Title : wrapper
-- Project : MUCTPI
----------------------------------------------------------------------------------------------------------------------
-- File : wrapper.vhd
-- Author : Marcos Oliveira
-- Company : CERN
-- Created : 2018-12-05
-- Last update: 2018-12-12
-- Platform : Vivado 2017.2 and Mentor Modelsim SE-64 10.4a
-- Standard : VHDL'93/02
----------------------------------------------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2018 CERN
----------------------------------------------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2018-12-05 1.0 msilvaol Created
----------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.math_real.all;
use work.bitonic_sorter_pkg.all;
entity wrapper is
generic(
I : natural := 16;
O : natural := 16;
delay : natural := 3 -- delay in clock cycles for pipeline register
);
port(
clk_wrapper : in std_logic;
clk : in std_logic;
input : in std_logic;
output : out std_logic);
attribute syn_loc : string;
attribute syn_pad_type : string;
attribute syn_loc of clk_wrapper :signal is"AU33";
attribute syn_loc of clk :signal is"AV33";
attribute syn_loc of input :signal is"AN32";
attribute syn_loc of output :signal is"AU31";
attribute syn_pad_type of clk_wrapper : signal is "LVCMOS18";
attribute syn_pad_type of clk : signal is "LVCMOS18";
attribute syn_pad_type of input : signal is "LVCMOS18";
attribute syn_pad_type of output : signal is "LVCMOS18";
end entity wrapper;
architecture rtl of wrapper is
--constants
constant i_width : integer := I*word_width;
constant o_width_desired : integer := O*word_width;
constant log4_o_width : integer := integer(ceil(log(real(o_width_desired), real(4))));
constant o_width : integer := 4**log4_o_width;
--components
component lfsr is
generic (
WIDTH : natural);
port (
clock : in std_logic;
input_bit : in std_logic;
output_vector : out std_logic_vector(WIDTH-1 downto 0));
end component lfsr;
component reducer is
generic (
input_width_log4 : natural);
port (
clock : in std_logic;
input_vector : in std_logic_vector(4**input_width_log4-1 downto 0);
output_bit : out std_logic);
end component reducer;
signal input_vector : std_logic_vector(i_width-1 downto 0) := (others => '0');
signal input_slr : std_logic_vector(i_width-1 downto 0) := (others => '0');
signal output_vector : std_logic_vector(o_width-1 downto 0) := (others => '0');
signal output_slr : std_logic_vector(o_width-1 downto 0) := (others => '0');
signal muon_cand : muon_a(0 to I-1);
signal top_cand : muon_a(0 to O-1);
signal source_valid : std_logic;
attribute DONT_TOUCH : string;
attribute DONT_TOUCH of lsfr_1 : label is "TRUE";
attribute DONT_TOUCH of reducer_1 : label is "TRUE";
--attribute DONT_TOUCH of muon_sorter_1 : label is "TRUE";
-- attribute KEEP : string;
-- attribute KEEP of muon_cand : signal is "TRUE";
-- attribute KEEP of top_cand : signal is "TRUE";
begin -- architecture rtl
lsfr_1 : lfsr
generic map (
WIDTH => i_width)
port map (
clock => clk_wrapper,
input_bit => input,
output_vector => input_vector);
shift_reg_tap_i : entity work.shift_reg_tap
generic map (
dw => i_width,
tw => 2)
port map (
clk => clk,
ce => '1',
tap => (others => '1'),
input => input_vector,
output => input_slr);
shift_reg_tap_o : entity work.shift_reg_tap
generic map (
dw => o_width,
tw => 2)
port map (
clk => clk,
ce => '1',
tap => (others => '1'),
input => output_vector,
output => output_slr);
reducer_1 : reducer
generic map (
input_width_log4 => log4_o_width)
port map (
clock => clk_wrapper,
input_vector => output_slr,
output_bit => output);
----------------------------------------------------------------------------------------------------------------------
-- Logic being tested
----------------------------------------------------------------------------------------------------------------------
muon_cand <= to_muon(input_slr, I);
output_vector(O*word_width-1 downto 0) <= to_stdv(top_cand, O);
dut_inst : bitonic_sort
generic map (
WIDTH => I,
DIR = > 1)
port map (
clk => clk,
m => muon_cand,
q => top_cand);
end architecture rtl;
\ No newline at end of file
#-- Synopsys, Inc.
#-- Version O-2018.09
#-- Project file D:\mygitlab\sorting\syn\I016_O016_D000_BUCKET-freq80retfan10000\rev_1\run_options.txt
#-- Written on Sat Feb 23 00:02:15 2019
#project files
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/MuctpiDataTypes.vhd"
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/MuctpiFunctions.vhd"
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/muon_sorter_bucket.vhd"
add_file -constraint "D:/mygitlab/sorting/src/xdc/clock_80.sdc"
add_file -constraint "D:/mygitlab/sorting/src/xdc/muon_sorter.sdc"
#implementation: "rev_1"
impl -add rev_1 -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#
#implementation parameter settings
set_option -hdl_param -set I 16
set_option -hdl_param -set O 16
set_option -hdl_param -set delay 0
set_option -hdl_param -set num_in 16
set_option -hdl_param -set num_out 16
set_option -include_path {../}
set_option -library_path {../}
#pr_1 attributes
set_option -job pr_1 -add par
#device options
set_option -technology VIRTEX-ULTRASCALEPLUS-FPGAS
set_option -part XCVU9P
set_option -package FLGC2104
set_option -speed_grade -1-e
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.muon_sorter_bucket"
# hdl_compiler_options
set_option -distributed_compile 1
# mapper_without_write_options
set_option -frequency 80
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 1
set_option -write_vhdl 0
# xilinx_options
set_option -rw_check_on_ram 1
set_option -optimize_ngc 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 1
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Virtex UltraScale+ FPGAs
set_option -enable_prepacking 1
set_option -use_vivado 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
# Compiler Options
set_option -vhdl2008 1
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "../rev_1/muon_sorter_bucket.edf"
#design plan options
impl -active "rev_1"
#-- Synopsys, Inc.
#-- Version O-2018.09
#-- Project file D:\mygitlab\sorting\syn\mux_AW012_DW032_D000-freq160retfan1000\rev_1\run_options.txt
#-- Written on Thu Feb 21 06:09:54 2019
#project files
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/mux/mux_pkg.vhd"
add_file -vhdl -lib work "D:/mygitlab/sorting/src/rtl/mux/mux.vhd"
#implementation: "rev_1"
impl -add rev_1 -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#
#implementation parameter settings
set_option -hdl_param -set AW 12
set_option -hdl_param -set DW 32
set_option -hdl_param -set delay 0
set_option -include_path {../}
set_option -library_path {../}
#pr_1 attributes
set_option -job pr_1 -add par
#device options
set_option -technology VIRTEX-ULTRASCALEPLUS-FPGAS
set_option -part XCVU9P
set_option -package FLGC2104
set_option -speed_grade -1-e
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.mux"
# hdl_compiler_options
set_option -distributed_compile 1
# mapper_without_write_options
set_option -frequency auto
set_option -srs_instrumentation 1
# mapper_options
set_option -write_verilog 1
set_option -write_vhdl 0
# xilinx_options
set_option -rw_check_on_ram 1
set_option -optimize_ngc 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 1
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Virtex UltraScale+ FPGAs
set_option -enable_prepacking 1
set_option -use_vivado 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
# Compiler Options
set_option -vhdl2008 1
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "../rev_1/mux.edf"
#design plan options
impl -active "rev_1"
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Wed Feb 20 03:47:09 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_high_fanout_nets -file fanout.txt -max_nets 200
| Design : wrapper_mux
| Device : xcvu9p
------------------------------------------------------------------------------------
High Fan-out Nets Information
1. Summary
----------
+----------------------------------------------------+--------+-------------+
| Net Name | Fanout | Driver Type |
+----------------------------------------------------+--------+-------------+
| shift_reg_tap_i/input_slr[131073]_repN_54 | 667 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_43 | 661 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_6 | 654 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_55 | 652 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_27 | 645 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_51 | 645 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_22 | 644 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_63 | 643 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_57 | 616 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_35 | 607 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_45 | 607 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_66 | 591 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_50 | 587 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_21 | 582 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_19 | 581 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_34 | 571 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_60 | 563 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_44 | 556 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN | 554 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_25 | 554 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_39 | 552 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_61 | 549 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_65 | 549 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_37 | 547 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_71 | 543 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_18 | 533 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_38 | 530 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_33 | 527 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_55 | 515 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_38 | 508 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_39 | 507 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_31 | 506 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_47 | 503 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_33 | 502 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_4 | 490 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_7 | 488 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_44 | 487 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_11 | 482 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_74 | 482 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_43 | 482 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_28 | 469 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_18 | 468 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_69 | 467 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_24 | 465 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_64 | 465 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_15 | 461 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_29 | 461 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_36 | 461 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_21 | 455 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_46 | 454 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_16 | 453 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_63 | 452 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_40 | 451 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_49 | 439 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_37 | 436 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_71 | 435 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_58 | 428 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_40 | 427 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_41 | 426 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_56 | 426 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_14 | 420 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_47 | 419 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_58 | 418 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_31 | 416 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_32 | 411 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_17 | 410 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_41 | 407 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_48 | 406 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_6 | 406 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_28 | 405 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_52 | 402 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_20 | 401 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_53 | 398 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_20 | 393 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_12 | 393 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_56 | 390 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_30 | 389 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_3 | 388 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_61 | 386 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_62 | 382 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_65 | 381 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_70 | 380 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_68 | 378 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_35 | 375 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_26 | 374 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_53 | 369 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_66 | 368 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_1 | 365 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_12 | 365 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_64 | 364 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_57 | 362 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_2 | 361 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_29 | 360 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_16 | 359 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_30 | 357 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_50 | 355 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_14 | 354 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_73 | 353 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_52 | 349 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_9 | 348 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_10 | 347 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_69 | 347 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_15 | 345 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_5 | 344 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_42 | 337 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_2 | 336 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_9 | 333 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_67 | 333 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_72 | 332 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_8 | 332 | FDRE |
| shift_reg_tap_i/input_slr_rep_119_0 | 325 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN | 324 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_26 | 321 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_32 | 318 | FDRE |
| shift_reg_tap_i/input_slr[131074]_repN_45 | 311 | FDRE |
| shift_reg_tap_i/input_slr[131073]_repN_42 | 308 | FDRE |
| shift_reg_tap_i/input_slr_rep_rep_33_0 | 304 | FDRE |
| shift_reg_tap_i/input_slr_rep_108_0 | 302 | FDRE |<