Commit a1ac9942 authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
Browse files

Created script to generate synplify runs, fixed issues with non-desired SRL implementation

parent 9f19ae28
-------------------------------------------------------------------------------
-- Title : Muon canidate sorter
-- Project :
-------------------------------------------------------------------------------
-- File : muon_sorter.vhd
-- Author : Stefan Haas
-- Company : CERN PH-ATE
-- Created : 12-07-13
-- Last update: 2019-01-30
-- Platform : Windows XP
-- Standard : VHDL-2008
-------------------------------------------------------------------------------
-- Description: Sorts muon candiates by pT
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CERN PH-ATE
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 12-07-13 1.0 haass Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
use work.MuctpiDataTypes.all;
use work.MuctpiFunctions.all;
entity muon_sorter is
generic(num_in : integer := 32; -- candidates to be sorted
num_out : integer := 16; -- Number of sorted muons
delay : positive := 3); -- delay in clock cycles for pipeline register
port(clk : in std_logic;
sink_valid : in std_logic;
source_valid : out std_logic;
muon_cand : in MuonCandidateArray(0 to num_in - 1);
top_cand : out MuonCandidateArray(0 to num_out - 1));
end muon_sorter;
-------------------------------------------------------------------------------
architecture behavior of muon_sorter is
-- 2D matrix of std_logic
type std_logic_matrix is array (natural range <>) of std_logic_vector;
-- array of comparison matrices, one per output candidate
type pt_compare_matrix_t is array (integer range <>) of std_logic_matrix(0 to num_in - 1)(0 to num_in - 2);
-- not accepted by Synplify
-- constant all_greater : pt_compare_matrix_t'element'element := (others => '1');
constant all_greater : std_logic_vector(0 to num_in - 2) := (others => '1');
-- array of compare matrices, one per output candidate
signal pt_compare : pt_compare_matrix_t(top_cand'range);
-- array with flags for the highest candidate
signal max_pt : std_logic_matrix(0 to num_out - 1)(0 to num_in - 1);
signal top_cand_comb : MuonCandidateArray(0 to num_out - 1);
-- pipeline
type sr_t is array (integer range <>) of MuonCandidateArray(0 to num_out - 1);
signal sr : sr_t(0 to delay);
signal sr_v : std_logic_vector(0 to delay);
attribute shreg_extract : string;
attribute shreg_extract of sr : signal is "no";
attribute shreg_extract of sr_v : signal is "no";
begin
compare_p : process(all) is
begin -- process
-- generate a comparison matrix
for i in muon_cand'range loop
for j in muon_cand'range loop
-- generate the first half of the comparison matrix
if j < i then
-- comparison matrix for the top candidate
pt_compare(0)(i)(j) <= compare_pt(muon_cand(i).pt, muon_cand(j).pt);
-- derive the matrices for the next higher candidates
for k in 1 to num_out - 1 loop
-- invert the comparison result if either candidate is the highest one
pt_compare(k)(i)(j) <= pt_compare(k - 1)(i)(j) xor max_pt(k - 1)(i) xor max_pt(k - 1)(j);
end loop; -- k
-- derive the 2nd half from the 1st
elsif j > i then
for k in pt_compare'range loop
pt_compare(k)(i)(j - 1) <= not pt_compare(k)(j)(i);
end loop; -- k
end if;
end loop; -- j
-- find the top candidate, i.e. the one for which all comparisons are true
for k in max_pt'range loop
max_pt(k)(i) <= pt_compare(k)(i) ?= all_greater;
end loop; -- k
end loop; -- i
end process compare_p;
output_p : process(all)
variable muon : MuonCandidate;
variable enable : std_logic;
begin -- process
--wait until rising_edge(clk);
-- assign the highset pt candidate index to the corresponding output
for k in top_cand'range loop
muon := (sector => X"0", pt => X"0", roi => X"00");
for i in muon_cand'range loop
-- there can only be one highest pt candidate, so ne can use a logical OR to implement a multiplexer
-- enable := pt_compare(k)(i) ?= all_greater;
enable := max_pt(k)(i);
muon.pt := muon.pt or (enable and muon_cand(i).pt);
muon.sector := muon.sector or (enable and muon_cand(i).sector);
muon.roi := muon.roi or (enable and muon_cand(i).roi);
end loop;
top_cand_comb(k) <= muon;
end loop; -- k
end process output_p;
sr_p : process(all) is
begin
sr(0) <= top_cand_comb;
sr_v(0) <= sink_valid;
if rising_edge(clk) then
for i in 1 to delay loop
sr(i) <= sr(i - 1);
sr_v(i) <= sr_v(i - 1);
end loop;
end if;
end process sr_p;
top_cand <= sr(delay);
source_valid <= sr_v(delay);
end behavior;
-------------------------------------------------------------------------------
-- Title : Muon canidate sorter
-- Project :
-------------------------------------------------------------------------------
-- File : muon_sorter.vhd
-- Author : Stefan Haas
-- Company : CERN PH-ATE
-- Created : 12-07-13
-- Last update: 2019-01-30
-- Platform : Windows XP
-- Standard : VHDL-2008
-------------------------------------------------------------------------------
-- Description: Sorts muon candiates by pT
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CERN PH-ATE
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 12-07-13 1.0 haass Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std_unsigned.all;
use work.MuctpiDataTypes.all;
use work.MuctpiFunctions.all;
entity muon_sorter is
generic(num_in : natural; -- candidates to be sorted
num_out : natural; -- Number of sorted muons
delay : natural); -- delay in clock cycles for pipeline register
port(clk : in std_logic;
sink_valid : in std_logic;
source_valid : out std_logic;
muon_cand : in MuonCandidateArray(0 to num_in - 1);
top_cand : out MuonCandidateArray(0 to num_out - 1));
end muon_sorter;
-------------------------------------------------------------------------------
architecture behavior of muon_sorter is
-- 2D matrix of std_logic
type std_logic_matrix is array (natural range <>) of std_logic_vector;
-- array of comparison matrices, one per output candidate
type pt_compare_matrix_t is array (integer range <>) of std_logic_matrix(0 to num_in - 1)(0 to num_in - 2);
-- not accepted by Synplify
-- constant all_greater : pt_compare_matrix_t'element'element := (others => '1');
constant all_greater : std_logic_vector(0 to num_in - 2) := (others => '1');
-- array of compare matrices, one per output candidate
signal pt_compare : pt_compare_matrix_t(top_cand'range);
-- array with flags for the highest candidate
signal max_pt : std_logic_matrix(0 to num_out - 1)(0 to num_in - 1);
signal top_cand_comb : MuonCandidateArray(0 to num_out - 1);
-- pipeline
type sr_t is array (integer range <>) of MuonCandidateArray(0 to num_out - 1);
signal sr : sr_t(0 to delay);
signal sr_v : std_logic_vector(0 to delay);
attribute shreg_extract : string;
attribute shreg_extract of sr : signal is "no";
attribute shreg_extract of sr_v : signal is "no";
attribute syn_srlstyle: string;
attribute syn_srlstyle of sr : signal is "registers";
attribute syn_srlstyle of sr_v : signal is "registers";
begin
compare_p : process(all) is
begin -- process
-- generate a comparison matrix
for i in muon_cand'range loop
for j in muon_cand'range loop
-- generate the first half of the comparison matrix
if j < i then
-- comparison matrix for the top candidate
pt_compare(0)(i)(j) <= compare_pt(muon_cand(i).pt, muon_cand(j).pt);
-- derive the matrices for the next higher candidates
for k in 1 to num_out - 1 loop
-- invert the comparison result if either candidate is the highest one
pt_compare(k)(i)(j) <= pt_compare(k - 1)(i)(j) xor max_pt(k - 1)(i) xor max_pt(k - 1)(j);
end loop; -- k
-- derive the 2nd half from the 1st
elsif j > i then
for k in pt_compare'range loop
pt_compare(k)(i)(j - 1) <= not pt_compare(k)(j)(i);
end loop; -- k
end if;
end loop; -- j
-- find the top candidate, i.e. the one for which all comparisons are true
for k in max_pt'range loop
max_pt(k)(i) <= pt_compare(k)(i) ?= all_greater;
end loop; -- k
end loop; -- i
end process compare_p;
output_p : process(all)
variable muon : MuonCandidate;
variable enable : std_logic;
begin -- process
--wait until rising_edge(clk);
-- assign the highset pt candidate index to the corresponding output
for k in top_cand'range loop
muon := (sector => X"0", pt => X"0", roi => X"00");
for i in muon_cand'range loop
-- there can only be one highest pt candidate, so ne can use a logical OR to implement a multiplexer
-- enable := pt_compare(k)(i) ?= all_greater;
enable := max_pt(k)(i);
muon.pt := muon.pt or (enable and muon_cand(i).pt);
muon.sector := muon.sector or (enable and muon_cand(i).sector);
muon.roi := muon.roi or (enable and muon_cand(i).roi);
end loop;
top_cand_comb(k) <= muon;
end loop; -- k
end process output_p;
sr_p : process(all) is
begin
sr(0) <= top_cand_comb;
sr_v(0) <= sink_valid;
if rising_edge(clk) then
for i in 1 to delay loop
sr(i) <= sr(i - 1);
sr_v(i) <= sr_v(i - 1);
end loop;
end if;
end process sr_p;
top_cand <= sr(delay);
source_valid <= sr_v(delay);
end behavior;
\ No newline at end of file
......@@ -46,6 +46,9 @@ architecture rtl of shift_reg_tap is
attribute shreg_extract : string;
attribute shreg_extract of sr : signal is "no";
attribute syn_srlstyle: string;
attribute syn_srlstyle of sr : signal is "registers";
begin -- architecture rtl
......@@ -64,4 +67,4 @@ begin -- architecture rtl
output <= sr(to_integer(unsigned(tap)));
end architecture rtl;
end architecture rtl;
\ No newline at end of file
......@@ -32,7 +32,7 @@ entity wrapper is
generic(
I : natural := 16;
O : natural := 16;
delay : positive := 3 -- delay in clock cycles for pipeline register
delay : natural := 3 -- delay in clock cycles for pipeline register
);
port(
......@@ -72,9 +72,9 @@ architecture rtl of wrapper is
end component reducer;
signal input_vector : std_logic_vector(i_width-1 downto 0) := (others => '0');
signal input_slr : std_logic;
signal input_slr : std_logic_vector(i_width-1 downto 0) := (others => '0');
signal output_vector : std_logic_vector(o_width-1 downto 0) := (others => '0');
signal output_slr : std_logic;
signal output_slr : std_logic_vector(o_width-1 downto 0) := (others => '0');
signal muon_cand : MuonCandidateArray(0 to I-1);
......@@ -95,43 +95,45 @@ architecture rtl of wrapper is
begin -- architecture rtl
shift_reg_tap_i : entity work.shift_reg_tap
generic map (
dw => 1,
tw => 3)
port map (
clk => clk_wrapper,
ce => '1',
tap => (others => '1'),
input(0) => input,
output(0) => input_slr);
lsfr_1 : lfsr
generic map (
WIDTH => i_width)
port map (
clock => clk_wrapper,
input_bit => input_slr,
input_bit => input,
output_vector => input_vector);
shift_reg_tap_i : entity work.shift_reg_tap
generic map (
dw => i_width,
tw => 4)
port map (
clk => clk_user,
ce => '1',
tap => (others => '1'),
input => input_vector,
output => input_slr);
shift_reg_tap_o : entity work.shift_reg_tap
generic map (
dw => o_width,
tw => 4)
port map (
clk => clk_user,
ce => '1',
tap => (others => '1'),
input => output_vector,
output => output_slr);
reducer_1 : reducer
generic map (
input_width_log4 => log4_o_width)
port map (
clock => clk_wrapper,
input_vector => output_vector,
output_bit => output_slr);
input_vector => output_slr,
output_bit => output);
shift_reg_tap_o : entity work.shift_reg_tap
generic map (
dw => 1,
tw => 3)
port map (
clk => clk_wrapper,
ce => '1',
tap => (others => '1'),
input(0) => output_slr,
output(0) => output);
----------------------------------------------------------------------------------------------------------------------
-- Logic being tested
......@@ -144,7 +146,7 @@ begin -- architecture rtl
end if;
end process;
muon_cand_c <= to_muon(input_vector, I);
muon_cand_c <= to_muon(input_slr, I);
output_vector(O*MuonCandidateLength-1 downto 0) <= to_stdv(top_cand, O);
muon_sorter_1 : entity work.muon_sorter
......@@ -160,5 +162,4 @@ begin -- architecture rtl
top_cand => top_cand);
end architecture rtl;
end architecture rtl;
\ No newline at end of file
project -new D:/mygitlab/sorting/syn/prjI016O16D00/wrapperI016O16D00.prj
add_file -vhdl D:/mygitlab/sorting/src/rtl/MuctpiDataTypes.vhd
add_file -vhdl D:/mygitlab/sorting/src/rtl/MuctpiFunctions.vhd
add_file -verilog D:/mygitlab/sorting/src/rtl/lfsr.sv
add_file -vhdl D:/mygitlab/sorting/src/rtl/muon_sorter.vhd
add_file -verilog D:/mygitlab/sorting/src/rtl/reducer.sv
add_file -vhdl D:/mygitlab/sorting/src/rtl/shift_reg_tap.vhd
add_file -vhdl D:/mygitlab/sorting/src/rtl/wrapper.vhd
add_file -constraint ../../src/xdc/wrapper.sdc
set_option -disable_io_insertion 0
set_option -part XCVU9P
set_option -package FLGC2104
set_option -vhdl2008 1
set_option -retiming 0
hdl_param -set I 16
hdl_param -set O 16
hdl_param -set delay 0
project -save D:/mygitlab/sorting/syn/prjI016O16D00/wrapperI016O16D00.prj
project -run compile
export_project -instance muon_sorter_1 -add_file {../src/rtl/MuctpiDataTypes.vhd ../src/rtl/MuctpiFunctions.vhd ../src/rtl/muon_sorter.vhd} -no_default_hdl -project D:/mygitlab/sorting/syn/prjI016O16D00/muon_sorter_1/muon_sorter_1.prj
project_data -active D:/mygitlab/sorting/syn/prjI016O16D00/muon_sorter_1/muon_sorter_1.prj
set_option -disable_io_insertion 1
set_option -part XCVU9P
set_option -package FLGC2104
set_option -vhdl2008 1
set_option -retiming 1
hdl_param -set num_in 16
hdl_param -set num_out 16
hdl_param -set delay 0
set_option -job pr_1 -add par
set_option -job pr_1 -option enable_run 0
add_file -constraint ../../../src/xdc/muon_sorter.sdc
project -save D:/mygitlab/sorting/syn/prjI016O16D00/muon_sorter_1/muon_sorter_1.prj
project_data -active D:/mygitlab/sorting/syn/prjI016O16D00/wrapperI016O16D00.prj
set_option -job par_1 -option enable_run 1
#impl -active rev_1
project -run
#run_tcl -fg D:/mygitlab/sorting/src/tcl/generate_syn_runs.tcl
# project_data -active D:/mygitlab/sorting/syn/muon_sorter_muon_sorter_1/muon_sorter_muon_sorter_1.prj
# set_option -disable_io_insertion 1
# set_option -part XCVU9P
# set_option -package FLGC2104
# set_option -vhdl2008 1
# set_option -retiming 1
# hdl_param -set num_in 16
# hdl_param -set num_out 16
# hdl_param -set delay 0
# set_option -job pr_1 -add par
# set_option -job pr_1 -option enable_run 0
# set_option -constraint D:/mygitlab/sorting/src/xdc/muon_sorter.sdc
# project -save D:/mygitlab/sorting/syn/muon_sorter_muon_sorter_1/muon_sorter_muon_sorter_1.prj
#impl -active muon_impl
# project -run
# project_data -active D:/mygitlab/sorting/syn/prjI016O16D00/wrapperI016O16D00.prj
#impl -active wrapper_impl
# project -run
\ No newline at end of file
set_property PACKAGE_PIN AU33 [get_ports clk_wrapper]
set_property PACKAGE_PIN AV33 [get_ports clk_user]
set_property PACKAGE_PIN AN32 [get_ports input]
set_property PACKAGE_PIN AU31 [get_ports output]
set_property IOSTANDARD LVCMOS18 [get_ports clk_wrapper]
set_property IOSTANDARD LVCMOS18 [get_ports clk_user]
set_property IOSTANDARD LVCMOS18 [get_ports input]
set_property IOSTANDARD LVCMOS18 [get_ports output]
create_clock -period 1000.000 -name clk_wrapper -waveform {0.000 500.000} [get_ports clk_wrapper]
create_clock -period 12.500 -name clk_user -waveform {0.000 6.250} [get_ports clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_wrapper] -group [get_clocks clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_user] -group [get_clocks clk_wrapper]
set_false_path -from [get_clocks clk_wrapper] -to [get_clocks clk_wrapper]
# not investigating timing yet
#set_false_path -from [get_clocks clk_user] -to [get_clocks clk_user]
set_property PACKAGE_PIN AU33 [get_ports clk_wrapper]
set_property PACKAGE_PIN AV33 [get_ports clk_user]
set_property PACKAGE_PIN AN32 [get_ports input]
set_property PACKAGE_PIN AU31 [get_ports output]
set_property IOSTANDARD LVCMOS18 [get_ports clk_wrapper]
set_property IOSTANDARD LVCMOS18 [get_ports clk_user]
set_property IOSTANDARD LVCMOS18 [get_ports input]
set_property IOSTANDARD LVCMOS18 [get_ports output]
create_clock -period 1000.000 -name clk_wrapper -waveform {0.000 500.000} [get_ports clk_wrapper]
create_clock -period 6.250 -name clk_user -waveform {0.000 3.125} [get_ports clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_wrapper] -group [get_clocks clk_user]
set_clock_groups -asynchronous -group [get_clocks clk_user] -group [get_clocks clk_wrapper]
set_false_path -from [get_clocks clk_wrapper] -to [get_clocks clk_wrapper]
# not investigating timing yet
#set_false_path -from [get_clocks clk_user] -to [get_clocks clk_user]
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