Commit ca7361fe authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
Browse files

Added new reports

parent 0fe46fb6
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Tue Feb 5 21:55:43 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_bus_skew -warn_on_violation -file wrapper_bus_skew_routed.rpt -pb wrapper_bus_skew_routed.pb -rpx wrapper_bus_skew_routed.rpx
| Design : wrapper
| Device : xcvu9p-flgc2104
| Speed File : -1 PRODUCTION 1.20 05-21-2018
| Temperature Grade : E
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Bus Skew Report
No bus skew constraints
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Tue Feb 5 21:43:54 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_control_sets -verbose -file wrapper_control_sets_placed.rpt
| Design : wrapper
| Device : xcvu9p
------------------------------------------------------------------------------------
Control Set Information
Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information
1. Summary
----------
+----------------------------------------------------------+-------+
| Status | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets | 2 |
| Unused register locations in slices containing registers | 0 |
+----------------------------------------------------------+-------+
2. Histogram
------------
+--------+--------------+
| Fanout | Control Sets |
+--------+--------------+
| 16+ | 2 |
+--------+--------------+
3. Flip-Flop Distribution
-------------------------
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 20380 | 1063 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 0 | 0 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
+--------------+-----------------------+------------------------+-----------------+--------------+
4. Detailed Control Set Information
-----------------------------------
+------------------------+---------------+------------------+------------------+----------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count |
+------------------------+---------------+------------------+------------------+----------------+
| clk_wrapper_IBUF_BUFG | | | 110 | 1196 |
| clk_IBUF_BUFG | | | 953 | 19184 |
+------------------------+---------------+------------------+------------------+----------------+
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Tue Feb 5 21:39:03 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_drc -file wrapper_drc_opted.rpt -pb wrapper_drc_opted.pb -rpx wrapper_drc_opted.rpx
| Design : wrapper
| Device : xcvu9p-flgc2104-1-e
| Speed File : -1
| Design State : Synthesized
------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Tue Feb 5 21:53:10 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_drc -file wrapper_drc_routed.rpt -pb wrapper_drc_routed.pb -rpx wrapper_drc_routed.rpx
| Design : wrapper
| Device : xcvu9p-flgc2104-1-e
| Speed File : -1
| Design State : Routed
---------------------------------------------------------------------------------------------------------------
Report DRC
Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS
1. REPORT SUMMARY
-----------------
Netlist: netlist
Floorplan: design_1
Design limits: <entire design considered>
Ruledeck: default
Max violations: <unlimited>
Violations found: 0
+------+----------+-------------+------------+
| Rule | Severity | Description | Violations |
+------+----------+-------------+------------+
+------+----------+-------------+------------+
2. REPORT DETAILS
-----------------
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Tue Feb 5 21:53:59 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_power -file wrapper_power_routed.rpt -pb wrapper_power_summary_routed.pb -rpx wrapper_power_routed.rpx
| Design : wrapper
| Device : xcvu9p-flgc2104-1-e
| Design State : routed
| Grade : extended
| Process : typical
| Characterization : Production
-------------------------------------------------------------------------------------------------------------------------------------------
Power Report
Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy
1. Summary
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 2.514 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.044 |
| Device Static (W) | 2.470 |
| Effective TJA (C/W) | 0.5 |
| Max Ambient (C) | 98.6 |
| Junction Temperature (C) | 26.4 |
| Confidence Level | Medium |
| Setting File | --- |
| Simulation Activity File | --- |
| Design Nets Matched | NA |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks | 0.042 | 4 | --- | --- |
| CLB Logic | <0.001 | 15718 | --- | --- |
| LUT as Logic | <0.001 | 5267 | 1182240 | 0.45 |
| Register | <0.001 | 10190 | 2364480 | 0.43 |
| Others | 0.000 | 15 | --- | --- |
| Signals | 0.001 | 15018 | --- | --- |
| I/O | <0.001 | 4 | 416 | 0.96 |
| Static Power | 2.470 | | | |
| Total | 2.514 | | | |
+----------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
------------------------
+------------+-------------+-----------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+------------+-------------+-----------+-------------+------------+
| Vccint | 0.850 | 0.859 | 0.051 | 0.808 |
| Vccint_io | 0.850 | 0.262 | 0.000 | 0.262 |
| Vccbram | 0.850 | 0.015 | 0.000 | 0.015 |
| Vccaux | 1.800 | 0.651 | 0.000 | 0.651 |
| Vccaux_io | 1.800 | 0.185 | 0.000 | 0.185 |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 |
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 |
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 |
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 |
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 |
| Vcco10 | 1.000 | 0.000 | 0.000 | 0.000 |
| Vccadc | 1.800 | 0.024 | 0.000 | 0.024 |
| MGTYAVcc | 0.900 | 0.000 | 0.000 | 0.000 |
| MGTYAVtt | 1.200 | 0.000 | 0.000 | 0.000 |
| MGTYVccaux | 1.800 | 0.000 | 0.000 | 0.000 |
+------------+-------------+-----------+-------------+------------+
1.3 Confidence Level
--------------------
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data | Confidence | Details | Action |
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High | Design is routed | |
| Clock nodes activity | High | User specified more than 95% of clocks | |
| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models | High | Device models are Production | |
| | | | |
| Overall confidence level | Medium | | |
+-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
2. Settings
-----------
2.1 Environment
---------------
+-----------------------+--------------------------+
| Ambient Temp (C) | 25.0 |
| ThetaJA (C/W) | 0.5 |
| Airflow (LFM) | 250 |
| Heat Sink | medium (Medium Profile) |
| ThetaSA (C/W) | 0.7 |
| Board Selection | medium (10"x10") |
| # of Board Layers | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0 |
+-----------------------+--------------------------+
2.2 Clock Constraints
---------------------
+-------------+-------------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------------+-------------+-----------------+
| clk | clk | 6.3 |
| clk_wrapper | clk_wrapper | 1000.0 |
+-------------+-------------+-----------------+
3. Detailed Reports
-------------------
3.1 By Hierarchy
----------------
+--------------------------------------------------+-----------+
| Name | Power (W) |
+--------------------------------------------------+-----------+
| wrapper | 0.044 |
| clk_IBUF_inst | <0.001 |
| clk_wrapper_IBUF_inst | <0.001 |
| lsfr_1 | <0.001 |
| lsfr_1_i_1 | <0.001 |
| muon_sorter_1 | 0.008 |
| mh_compare_pt_and_find_max_pt_hierarchical_0 | 0.003 |
| mh_compare_pt_0_1 | <0.001 |
| mh_compare_pt_1_and_find_max_1 | <0.001 |
| mh_multiplexor_1 | <0.001 |
| reducer_1 | <0.001 |
| shift_reg_tap_i | 0.017 |
| shift_reg_tap_o | 0.016 |
+--------------------------------------------------+-----------+
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 15717 :
# of nets not needing routing.......... : 694 :
# of internally routed nets........ : 694 :
# of routable nets..................... : 15023 :
# of fully routed nets............. : 15023 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :
This source diff could not be displayed because it is too large. You can view the blob instead.
Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
| Date : Tue Feb 5 21:43:54 2019
| Host : PCPHESEBE02 running 64-bit Service Pack 1 (build 7601)
| Command : report_utilization -file wrapper_utilization_placed.rpt -pb wrapper_utilization_placed.pb
| Design : wrapper
| Device : xcvu9pflgc2104-1
| Design State : Fully Placed
-----------------------------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. CLB Logic
1.1 Summary of Registers by Type
2. CLB Logic Distribution
3. BLOCKRAM
4. ARITHMETIC
5. I/O
6. CLOCK
7. ADVANCED
8. CONFIGURATION
9. Primitives
10. Black Boxes
11. Instantiated Netlists
12. SLR Connectivity and Clocking Utilization
13. SLR Connectivity Matrix
14. SLR CLB Logic and Dedicated Block Utilization
15. SLR IO Utilization
1. CLB Logic
------------
+-------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+-------+-------+-----------+-------+
| CLB LUTs | 5267 | 0 | 1182240 | 0.45 |
| LUT as Logic | 5267 | 0 | 1182240 | 0.45 |
| LUT as Memory | 0 | 0 | 591840 | 0.00 |
| CLB Registers | 10190 | 0 | 2364480 | 0.43 |
| Register as Flip Flop | 10190 | 0 | 2364480 | 0.43 |
| Register as Latch | 0 | 0 | 2364480 | 0.00 |
| CARRY8 | 0 | 0 | 147780 | 0.00 |
| F7 Muxes | 0 | 0 | 591120 | 0.00 |
| F8 Muxes | 0 | 0 | 295560 | 0.00 |
| F9 Muxes | 0 | 0 | 147780 | 0.00 |
+-------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 10190 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. CLB Logic Distribution
-------------------------
+-------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+------+-------+-----------+-------+
| CLB | 1231 | 0 | 147780 | 0.83 |
| CLBL | 572 | 0 | | |
| CLBM | 659 | 0 | | |
| LUT as Logic | 5267 | 0 | 1182240 | 0.45 |
| using O5 output only | 26 | | | |
| using O6 output only | 4995 | | | |
| using O5 and O6 | 246 | | | |
| LUT as Memory | 0 | 0 | 591840 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | |
| LUT as Shift Register | 0 | 0 | | |
| LUT Flip Flop Pairs | 2083 | 0 | 1182240 | 0.18 |
| fully used LUT-FF pairs | 98 | | | |
| LUT-FF pairs with one unused LUT output | 1957 | | | |
| LUT-FF pairs with one unused Flip Flop | 646 | | | |
| Unique Control Sets | 2 | | | |
+-------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. BLOCKRAM
-----------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 2160 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 2160 | 0.00 |
| RAMB18 | 0 | 0 | 4320 | 0.00 |
| URAM | 0 | 0 | 960 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E2 or one FIFO18E2. However, if a FIFO18E2 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E2
4. ARITHMETIC
-------------
+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0 | 0 | 6840 | 0.00 |
+-----------+------+-------+-----------+-------+
5. I/O
------
+------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------------+------+-------+-----------+-------+
| Bonded IOB | 4 | 4 | 416 | 0.96 |
| HPIOB_M | 4 | 4 | 192 | 2.08 |
| INPUT | 3 | | | |
| OUTPUT | 1 | | | |
| BIDIR | 0 | | | |
| HPIOB_S | 0 | 0 | 192 | 0.00 |
| HPIOB_SNGL | 0 | 0 | 32 | 0.00 |
| HPIOBDIFFINBUF | 0 | 0 | 720 | 0.00 |
| HPIOBDIFFOUTBUF | 0 | 0 | 720 | 0.00 |
| BITSLICE_CONTROL | 0 | 0 | 240 | 0.00 |
| BITSLICE_RX_TX | 0 | 0 | 1560 | 0.00 |
| BITSLICE_TX | 0 | 0 | 240 | 0.00 |
| RIU_OR | 0 | 0 | 120 | 0.00 |
+------------------+------+-------+-----------+-------+
6. CLOCK
--------
+----------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------+------+-------+-----------+-------+
| GLOBAL CLOCK BUFFERs | 2 | 0 | 1800 | 0.11 |
| BUFGCE | 2 | 0 | 720 | 0.28 |
| BUFGCE_DIV | 0 | 0 | 120 | 0.00 |
| BUFG_GT | 0 | 0 | 720 | 0.00 |
| BUFGCTRL* | 0 | 0 | 240 | 0.00 |
| PLL | 0 | 0 | 60 | 0.00 |
| MMCM | 0 | 0 | 30 | 0.00 |
+----------------------+------+-------+-----------+-------+
* Note: Each used BUFGCTRL counts as two global buffer resources. This table does not include global clocking resources, only buffer cell usage. See the Clock Utilization Report (report_clock_utilization) for detailed accounting of global clocking resource availability.
7. ADVANCED
-----------
+------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------------+------+-------+-----------+-------+
| CMACE4 | 0 | 0 | 9 | 0.00 |
| GTYE4_CHANNEL | 0 | 0 | 104 | 0.00 |
| GTYE4_COMMON | 0 | 0 | 26 | 0.00 |
| ILKNE4 | 0 | 0 | 9 | 0.00 |
| OBUFDS_GTE4 | 0 | 0 | 52 | 0.00 |
| OBUFDS_GTE4_ADV | 0 | 0 | 52 | 0.00 |
| PCIE40E4 | 0 | 0 | 6 | 0.00 |
| SYSMONE4 | 0 | 0 | 3 | 0.00 |
| LAGUNA Registers | 0 | 0 | 69120 | 0.00 |
| as TX_REG | 0 | | | |
| as RX_REG | 0 | | | |
+------------------+------+-------+-----------+-------+
8. CONFIGURATION
----------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 12 | 0.00 |
| DNA_PORTE2 | 0 | 0 | 3 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE4 | 0 | 0 | 1 | 0.00 |
| ICAPE3 | 0 | 0 | 2 | 0.00 |
| MASTER_JTAG | 0 | 0 | 3 | 0.00 |
| STARTUPE3 | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
9. Primitives
-------------
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| FDRE | 10190 | Register |
| LUT6 | 2851 | CLB |
| LUT5 | 1631 | CLB |
| LUT3 | 427 | CLB |
| LUT4 | 347 | CLB |
| LUT2 | 257 | CLB |
| INBUF | 3 | I/O |
| IBUFCTRL | 3 | Others |
| BUFGCE | 2 | Clock |
| OBUF | 1 | I/O |
+----------+-------+---------------------+
10. Black Boxes
---------------
+----------+------+
| Ref Name | Used |
+----------+------+
11. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
12. SLR Connectivity and Clocking Utilization
---------------------------------------------
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| | Total SLLs Used | (%)SLLs | BUFGs/BUFGCTRLs | BUFH/BUFHCEs | BUFRs | MMCMs |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| SLR2 | | | 0 | 0 | 0 | 0 |
| ||||||-> | 0 | 0.00 | | | | |
| SLR1 | | | 2 | 0 | 0 | 0 |
| ||||||-> | 0 | 0.00 | | | | |
| SLR0 | | | 0 | 0 | 0 | 0 |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
| Total | 0 | | 2 | 0 | 0 | 0 |
+----------+-----------------+---------+-----------------+--------------+-------+-------+
13. SLR Connectivity Matrix
---------------------------