Commit df0f18ea authored by Marcos Vinicius Silva Oliveira's avatar Marcos Vinicius Silva Oliveira
Browse files

new code

parent 45f1a535
...@@ -60,7 +60,7 @@ architecture behavior of muon_sorter is ...@@ -60,7 +60,7 @@ architecture behavior of muon_sorter is
signal top_cand_comb : MuonCandidateArray(0 to num_out - 1); signal top_cand_comb : MuonCandidateArray(0 to num_out - 1);
-- pipeline output -- pipeline
type sr_t is array (integer range <>) of MuonCandidateArray(0 to num_out - 1); type sr_t is array (integer range <>) of MuonCandidateArray(0 to num_out - 1);
...@@ -74,35 +74,18 @@ architecture behavior of muon_sorter is ...@@ -74,35 +74,18 @@ architecture behavior of muon_sorter is
attribute syn_srlstyle: string; attribute syn_srlstyle: string;
attribute syn_srlstyle of sr : signal is "registers"; attribute syn_srlstyle of sr : signal is "registers";
attribute syn_srlstyle of sr_v : signal is "registers"; attribute syn_srlstyle of sr_v : signal is "registers";
-- pipeline input
type in_sr_t is array (integer range <>) of MuonCandidateArray(0 to num_in - 1);
signal in_sr : sr_t(0 to delay);
signal in_sr_v : std_logic_vector(0 to delay);
attribute shreg_extract : string;
attribute shreg_extract of in_sr : signal is "no";
attribute shreg_extract of in_sr_v : signal is "no";
attribute syn_srlstyle: string;
attribute syn_srlstyle of in_sr : signal is "registers";
attribute syn_srlstyle of in_sr_v : signal is "registers";
signal muon_cand_sr : MuonCandidateArray(0 to num_in - 1);
signal sink_valid_sr : std_logic;
begin begin
compare_p : process(all) is compare_p : process(all) is
begin -- process begin -- process
-- generate a comparison matrix -- generate a comparison matrix
for i in muon_cand_sr'range loop for i in muon_cand'range loop
for j in muon_cand_sr'range loop for j in muon_cand'range loop
-- generate the first half of the comparison matrix -- generate the first half of the comparison matrix
if j < i then if j < i then
-- comparison matrix for the top candidate -- comparison matrix for the top candidate
pt_compare(0)(i)(j) <= compare_pt(muon_cand_sr(i).pt, muon_cand_sr(j).pt); pt_compare(0)(i)(j) <= compare_pt(muon_cand(i).pt, muon_cand(j).pt);
-- derive the matrices for the next higher candidates -- derive the matrices for the next higher candidates
for k in 1 to num_out - 1 loop for k in 1 to num_out - 1 loop
-- invert the comparison result if either candidate is the highest one -- invert the comparison result if either candidate is the highest one
...@@ -130,13 +113,13 @@ begin ...@@ -130,13 +113,13 @@ begin
-- assign the highset pt candidate index to the corresponding output -- assign the highset pt candidate index to the corresponding output
for k in top_cand'range loop for k in top_cand'range loop
muon := (sector => X"0", pt => X"0", roi => X"00"); muon := (sector => X"0", pt => X"0", roi => X"00");
for i in muon_cand_sr'range loop for i in muon_cand'range loop
-- there can only be one highest pt candidate, so ne can use a logical OR to implement a multiplexer -- there can only be one highest pt candidate, so ne can use a logical OR to implement a multiplexer
-- enable := pt_compare(k)(i) ?= all_greater; -- enable := pt_compare(k)(i) ?= all_greater;
enable := max_pt(k)(i); enable := max_pt(k)(i);
muon.pt := muon.pt or (enable and muon_cand_sr(i).pt); muon.pt := muon.pt or (enable and muon_cand(i).pt);
muon.sector := muon.sector or (enable and muon_cand_sr(i).sector); muon.sector := muon.sector or (enable and muon_cand(i).sector);
muon.roi := muon.roi or (enable and muon_cand_sr(i).roi); muon.roi := muon.roi or (enable and muon_cand(i).roi);
end loop; end loop;
top_cand_comb(k) <= muon; top_cand_comb(k) <= muon;
end loop; -- k end loop; -- k
...@@ -145,33 +128,17 @@ begin ...@@ -145,33 +128,17 @@ begin
sr_p : process(all) is sr_p : process(all) is
begin begin
sr(0) <= top_cand_comb;
sr_v(0) <= sink_valid;
if rising_edge(clk) then if rising_edge(clk) then
for i in 1 to delay loop for i in 1 to delay loop
sr(i) <= sr(i - 1); sr(i) <= sr(i - 1);
sr_v(i) <= sr_v(i - 1); sr_v(i) <= sr_v(i - 1);
end loop; end loop;
end if; end if;
if rising_edge(clk) then
for i in 1 to delay loop
in_sr(i) <= sr(i - 1);
in_sr_v(i) <= sr_v(i - 1);
end loop;
end if;
end process sr_p; end process sr_p;
sr(0) <= top_cand_comb;
sr_v(0) <= sink_valid_sr;
in_sr(0) <= muon_cand;
in_sr_v(0) <= sink_valid;
top_cand <= sr(delay); top_cand <= sr(delay);
source_valid <= sr_v(delay); source_valid <= sr_v(delay);
muon_cand_sr <= in_sr(delay);
sink_valid_sr <= in_sr_v(delay);
end behavior; end behavior;
\ No newline at end of file
...@@ -116,7 +116,7 @@ begin -- architecture rtl ...@@ -116,7 +116,7 @@ begin -- architecture rtl
shift_reg_tap_i : entity work.shift_reg_tap shift_reg_tap_i : entity work.shift_reg_tap
generic map ( generic map (
dw => i_width, dw => i_width,
tw => 4) tw => 2)
port map ( port map (
clk => clk, clk => clk,
ce => '1', ce => '1',
...@@ -127,7 +127,7 @@ begin -- architecture rtl ...@@ -127,7 +127,7 @@ begin -- architecture rtl
shift_reg_tap_o : entity work.shift_reg_tap shift_reg_tap_o : entity work.shift_reg_tap
generic map ( generic map (
dw => o_width, dw => o_width,
tw => 4) tw => 2)
port map ( port map (
clk => clk, clk => clk,
ce => '1', ce => '1',
......
proc create_run {I O D {run 1} opt} { proc create_run {I O D {run 1} opt} {
puts "Creating run with I = $I, O = $O, D = $D" puts "Creating run with I = $I, O = $O, D = $D"
set prjpre [format "I%03d_O%03d_D%03d_IORET" $I $O $D] set prjpre [format "I%03d_O%03d_D%03d_SHORTSR" $I $O $D]
set prjname [format "%s-%s" $prjpre $opt] set prjname [format "%s-%s" $prjpre $opt]
set basepath "D:/mygitlab/sorting" set basepath "D:/mygitlab/sorting"
set prjpath [format "%s/syn/%s/wrapper_%s.prj" $basepath $prjname $prjname] set prjpath [format "%s/syn/%s/wrapper_%s.prj" $basepath $prjname $prjname]
...@@ -170,7 +170,7 @@ proc range {from to {step 1}} { ...@@ -170,7 +170,7 @@ proc range {from to {step 1}} {
} }
set cfgs [] set cfgs []
set opts [list freq320retfan10000 freq320retfan16 freq160retfan10000 freq160retfan16 freq80retfan10000 freq80retfan16 freq40retfan10000 freq40retfan16] set opts [list freq320retfan10000 freq160retfan10000 freq80retfan10000 freq80retfan16 freq40retfan10000 freq40retfan16]
#lappend cfgs [list 16 16 [range 0 2]] #lappend cfgs [list 16 16 [range 0 2]]
#lappend cfgs [list 16 2 [range 0 2]] #lappend cfgs [list 16 2 [range 0 2]]
lappend cfgs [list 16 16 [range 0 3]] lappend cfgs [list 16 16 [range 0 3]]
......
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