From ad02ac0e1759aef968b921fac5a5ef265e7ce36b Mon Sep 17 00:00:00 2001
From: Stewart Martin-Haugh <smh@cern.ch>
Date: Tue, 9 Jan 2018 13:47:32 +0100
Subject: [PATCH] Simplify conditions setup
Former-commit-id: fd5ccd75f5a1560bacc9f8284db4fc84aa019d53
---
.../TrigValidation/TrigUpgradeTest/share/IDCalo.py | 1 +
.../TrigUpgradeTest/share/mu.withViews.py | 3 ++-
.../TrigUpgradeTest/share/testHLT_MT.py | 11 +----------
3 files changed, 4 insertions(+), 11 deletions(-)
diff --git a/Trigger/TrigValidation/TrigUpgradeTest/share/IDCalo.py b/Trigger/TrigValidation/TrigUpgradeTest/share/IDCalo.py
index 0fbe00acc7f..0594b9b96a2 100644
--- a/Trigger/TrigValidation/TrigUpgradeTest/share/IDCalo.py
+++ b/Trigger/TrigValidation/TrigUpgradeTest/share/IDCalo.py
@@ -14,6 +14,7 @@ if globalflags.InputFormat.is_bytestream():
# ----------------------------------------------------------------
# Setup Views
# ----------------------------------------------------------------
+from AthenaCommon.AlgSequence import AthSequencer
viewSeq = AthSequencer("AthViewSeq", Sequential=True, ModeOR=False, StopOverride=False)
topSequence += viewSeq
diff --git a/Trigger/TrigValidation/TrigUpgradeTest/share/mu.withViews.py b/Trigger/TrigValidation/TrigUpgradeTest/share/mu.withViews.py
index 2efa5c2ee2f..0a0a84f04ff 100644
--- a/Trigger/TrigValidation/TrigUpgradeTest/share/mu.withViews.py
+++ b/Trigger/TrigValidation/TrigUpgradeTest/share/mu.withViews.py
@@ -62,8 +62,9 @@ if TriggerFlags.doMuon:
from RecExConfig.RecFlags import rec
if doL2SA:
- from ViewAlgs.ViewAlgsConf import EventViewCreatorAlgorithm
+ from AthenaCommon.AlgSequence import AthSequencer
l2MuViewNode = AthSequencer("l2MuViewNode", Sequential=False, ModeOR=False, StopOverride=False)
+ from ViewAlgs.ViewAlgsConf import EventViewCreatorAlgorithm
l2MuViewsMaker = EventViewCreatorAlgorithm("l2MuViewsMaker", OutputLevel=DEBUG)
l2MuViewsMaker.ViewFallThrough = True
diff --git a/Trigger/TrigValidation/TrigUpgradeTest/share/testHLT_MT.py b/Trigger/TrigValidation/TrigUpgradeTest/share/testHLT_MT.py
index 205c81c2059..a0d63dbe0c8 100644
--- a/Trigger/TrigValidation/TrigUpgradeTest/share/testHLT_MT.py
+++ b/Trigger/TrigValidation/TrigUpgradeTest/share/testHLT_MT.py
@@ -228,16 +228,7 @@ for mod in modifierList:
#--------------------------------------------------------------
# Conditions setup.
#--------------------------------------------------------------
-from IOVSvc.IOVSvcConf import CondSvc
-svcMgr += CondSvc()
-
-from AthenaCommon.AlgSequence import AthSequencer
-condSeq = AthSequencer("AthCondSeq")
-
-from IOVSvc.IOVSvcConf import CondInputLoader
-condSeq += CondInputLoader("CondInputLoader")
-
-from IOVDbSvc.CondDB import conddb
+from IOVDbSvc.CondDB import conddb #This import will also set up CondInputLoader
conddb.setGlobalTag(globalflags.ConditionsTag())
from AthenaCommon.AlgSequence import AlgSequence
--
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